From: Jason Lou <yun....@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790
Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (the tool link: https://github.com/mdkinney/edk2) Signed-off-by: Jason Lou <yun....@intel.com> Cc: Ray Ni <ray...@intel.com> Cc: Eric Dong <eric.d...@intel.com> Cc: Laszlo Ersek <ler...@redhat.com> Cc: Rahul Kumar <rahul1.ku...@intel.com> --- UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm | 4 +-- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm | 11 +++++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm | 9 +++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 14 +++++------ UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm | 26 ++++++++++---------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +-- 10 files changed, 42 insertions(+), 42 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm index 66f8857fc0..1bde01c571 100644 --- a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm +++ b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ;* -;* Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +;* Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR> ;* SPDX-License-Identifier: BSD-2-Clause-Patent ;* ;* CpuAsm.nasm @@ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector): push rcx lea rax, [setCodeSelectorLongJump] push rax - o64 retf + retfq setCodeSelectorLongJump: ret diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm index 58d5312899..f3ecb5fed4 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,12 +32,13 @@ ALIGN 8 ; exception handler stub table ; AsmIdtVectorBegin: +%assign Vector 0 %rep 32 - db 0x6a ; push #VectorNum - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum + push byte %[Vector]; push eax mov eax, ASM_PFX(CommonInterruptEntry) jmp eax +%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -287,7 +288,7 @@ ErrorCodeAndVectorOnStack: test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. ; edx still contains result from CPUID above jz .3 - db 0xf, 0xae, 0x7 ;fxsave [edi] + fxsave [edi] .3: ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear @@ -320,7 +321,7 @@ ErrorCodeAndVectorOnStack: ; are supported test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .4 - db 0xf, 0xae, 0xe ; fxrstor [esi] + fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm index dd3f74d2aa..48a6aa4a97 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -79,8 +79,7 @@ AsmExceptionEntryBegin: DoIret%[Vector]: iretd ASM_PFX(ExceptionTaskSwtichEntry%[Vector]): - db 0x6a ; push #VectorNum - db %[Vector] + push byte %[Vector] mov eax, ASM_PFX(CommonTaskSwtichEntryPoint) call eax mov esp, eax ; Restore stack top @@ -244,7 +243,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): clts sub esp, 512 mov edi, esp - db 0xf, 0xae, 0x7 ;fxsave [edi] + fxsave [edi] .3: ;; UINT32 ExceptionData; @@ -277,7 +276,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .4 mov esi, esp - db 0xf, 0xae, 0xe ; fxrstor [esi] + fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 2a5545ecfd..fb23d28b13 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2012 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,12 +32,13 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin: +%assign Vector 0 %rep 32 - db 0x6a ; push #VectorNum - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum + push byte %[Vector] push rax mov rax, ASM_PFX(CommonInterruptEntry) jmp rax +%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -257,7 +258,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp - db 0xf, 0xae, 0x7 ;fxsave [rdi] + fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -284,7 +285,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - db 0xf, 0xae, 0xE ; fxrstor [rsi] + fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; @@ -371,8 +372,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS - DB 0x48 ; prefix to composite "retq" with next "retf" - retf ; far return + retfq DoIret: iretq diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm index 84a12ddb88..df720f6c75 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2012 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -54,12 +54,13 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin: +%assign Vector 0 %rep 32 - db 0x6a ; push #VectorNum - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum + push byte %[Vector] push rax mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry) jmp rax +%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -280,7 +281,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp - db 0xf, 0xae, 0x7 ;fxsave [rdi] + fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -335,15 +336,15 @@ DrFinish: jz CetDone ; SSP should be 0xFC0 at this point mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor shadow stack token - INCSSP_RAX ; After this SSP should be 0xFE0 - SAVEPREVSSP ; now the shadow stack restore token will be created at 0xFB8 - READSSP_RAX ; Read new SSP, SSP should be 0xFE8 + incsspq rax ; After this SSP should be 0xFE0 + saveprevssp ; now the shadow stack restore token will be created at 0xFB8 + rdsspq rax ; Read new SSP, SSP should be 0xFE8 sub rax, 0x10 - CLRSSBSY_RAX ; Clear token at 0xFD8, SSP should be 0 after this + clrssbsy [rax] ; Clear token at 0xFD8, SSP should be 0 after this sub rax, 0x20 - RSTORSSP_RAX ; Restore to token at 0xFB8, new SSP will be 0xFB8 + rstorssp [rax] ; Restore to token at 0xFB8, new SSP will be 0xFB8 mov rax, 0x01 ; Pop off the new save token created - INCSSP_RAX ; SSP should be 0xFC0 now + incsspq rax ; SSP should be 0xFC0 now CetDone: cli @@ -353,7 +354,7 @@ CetDone: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - db 0xf, 0xae, 0xE ; fxrstor [rsi] + fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; @@ -440,8 +441,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS - DB 0x48 ; prefix to composite "retq" with next "retf" - retf ; far return + retfq DoIret: iretq diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm index f7f2937faf..30ad94d341 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -345,7 +345,7 @@ BITS 64 ; ; Far return into 32-bit mode ; -o64 retf + retfq BITS 32 CompatMode: @@ -507,7 +507,7 @@ NoSevEs: ; ; Far return into 32-bit mode ; -o64 retf + retfq BITS 32 PmEntry: diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm index 0919d6d05f..ee604e89a0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------- @@ -13,7 +13,7 @@ ASM_PFX(DisableCet): ; Skip the pushed data for call mov eax, 1 - INCSSP_EAX + incsspd eax mov eax, cr4 btr eax, 23 ; clear CET diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 167f5e14db..5d38c1f55b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; @@ -252,7 +252,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET mov cr4, eax - SETSSBSY + setssbsy CetDone: diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm index 3240f9d974..f23ad91132 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------- @@ -14,7 +14,7 @@ ASM_PFX(DisableCet): ; Skip the pushed data for call mov rax, 1 - INCSSP_RAX + incsspq rax mov rax, cr4 btr eax, 23 ; clear CET diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 0e154e5db9..f6712ce594 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; @@ -279,7 +279,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET mov cr4, rax - SETSSBSY + setssbsy CetDone: -- 2.28.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85227): https://edk2.groups.io/g/devel/message/85227 Mute This Topic: https://groups.io/mt/88008078/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
