Hi Khassim, Thanks for the new serie. I have some comments about the PCDs:
On 12/14/21 8:43 PM, Khasim Mohammed via groups.io wrote: > This patch enables CCIX root complex support by updating > the root complex node info in PciHostBridge library. > The corresponding PCDs are updated. > > Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28 The 'Change-Id' should be removed I think. > Signed-off-by: Khasim Syed Mohammed <khasim.moham...@arm.com> > --- > .../ConfigurationManager.c | 6 +- > .../ConfigurationManagerDxe.inf | 4 +- > Platform/ARM/N1Sdp/N1SdpPlatform.dec | 10 ++- > Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 - > .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++-- > .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++- > .../Library/PlatformLib/PlatformLib.inf | 1 + > .../Library/PlatformLib/PlatformLibMem.c | 4 +- > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 10 +-- > 9 files changed, 91 insertions(+), 27 deletions(-) > > diff --git > a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c > > b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c > index 9c91372c11..1998c44e63 100644 > --- > a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c > +++ > b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c > @@ -1047,21 +1047,21 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = { > { > // PCIe ECAM > { > - 0x70000000, // Base Address > + FixedPcdGet64 (PcdPcieExpressBaseAddress), // Base Address > 0x0, // Segment Group Number > 0x0, // Start Bus Number > 17 // End Bus Number For the 3 PCI interfaces (PCIe, remote PCI and CCIX), I think we can also use the Pcds for the min/max bus numbers: gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax I think a Pcd could also be created for each Segment Group Number, as for instance: gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentGroup Indeed, the segment number is also hard coded in the objects at: Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl Name (_SEG, Pcd(...)) // PCI Segment Group number Name (_BBN, Pcd(...)) // PCI Base Bus Number > }, > // CCIX ECAM > { > - 0x68000000, // Base Address > + FixedPcdGet32 (PcdCcixExpressBaseAddress), // Base Address > 0x1, // Segment Group Number > 0x0, // Start Bus Number > 17 // End Bus Number > }, > //Remote Chip PCIe ECAM > { > - 0x40070000000, // Base Address > + FixedPcdGet64 (PcdRemotePcieBaseAddress), // Base Address > 0x2, // Segment Group Number > 0x0, // Start Bus Number > 17 // End Bus Number > diff --git > a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf > > b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf > index 027a4202ff..84543e2f95 100644 > --- > a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf > +++ > b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf > @@ -76,8 +76,6 @@ > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate > > - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress > - > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace > gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > > @@ -91,6 +89,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize > @@ -158,6 +157,7 @@ > gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase > > # Remote PCIe > + gArmN1SdpTokenSpaceGuid.PcdRemotePcieBaseAddress > gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation > gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation > gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec > b/Platform/ARM/N1Sdp/N1SdpPlatform.dec > index 2ab6c20dcc..ed7ea44d0d 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec > @@ -34,9 +34,6 @@ > gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 > gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 > > - # PCIe > - > gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007 > - > # External memory > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029 > > @@ -94,6 +91,7 @@ > gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049 > > # Remote Chip PCIe > - > gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A > - > gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B > - > gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C > + > gArmN1SdpTokenSpaceGuid.PcdRemotePcieBaseAddress|0x40070000000|UINT64|0x0000004A > + > gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004B > + > gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004C > + > gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004D > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > index 7488bdc036..cb2049966c 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > @@ -127,7 +127,6 @@ > gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 > > # PCIe > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 > gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 > gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE > > diff --git > a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > index 9332939f63..c3a14a6c17 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -1,7 +1,7 @@ > /** @file > * PCI Host Bridge Library instance for ARM Neoverse N1 platform > * > -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR> > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -16,6 +16,8 @@ > #include <Protocol/PciHostBridgeResourceAllocation.h> > #include <Protocol/PciRootBridgeIo.h> > > +#define ROOT_COMPLEX_NUM 2 > + > GLOBAL_REMOVE_IF_UNREFERENCED > STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { > L"Mem", L"I/O", L"Bus" > @@ -28,7 +30,7 @@ typedef struct { > } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > #pragma pack () > > -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { > +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH > mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = { > // PCIe > { > { > @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH > mEfiPciRootBridgeDevicePath[] = { > 0 > } > } > - } > + }, > + //CCIX > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A09), // CCIX > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > }; > > -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { > +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = { > { > 0, // Segment > 0, // Supports > @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { > 0 > }, > (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] > - } > + }, > + { > + 1, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { > + // Bus > + FixedPcdGet32 (PcdCcixBusMin), > + FixedPcdGet32 (PcdCcixBusMax) > + }, { > + // Io > + FixedPcdGet64 (PcdCcixIoBase), > + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1 > + }, { > + // Mem > + FixedPcdGet32 (PcdCcixMmio32Base), > + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) > - 1 > + }, { > + // MemAbove4G > + FixedPcdGet64 (PcdCcixMmio64Base), > + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) > - 1 > + }, { > + // PMem > + MAX_UINT64, > + 0 > + }, { > + // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] > + }, > }; > > /** > diff --git > a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > index 3ff1c592f2..3356c3ad35 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -1,7 +1,7 @@ > ## @file > # PCI Host Bridge Library instance for ARM Neoverse N1 platform. > # > -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -42,6 +42,15 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size > > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size > + > [Protocols] > gEfiCpuIo2ProtocolGuid > > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > index 8e2154aadf..96e590cdd8 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > @@ -43,6 +43,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > index 1c4a445c5e..339fa07b32 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Attributes = > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > // PCIe ECAM Configuration Space > - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 > (PcdPciExpressBaseAddress); > - VirtualMemoryTable[Index].VirtualBase = PcdGet64 > (PcdPciExpressBaseAddress); > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 > (PcdPcieExpressBaseAddress); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 > (PcdPcieExpressBaseAddress); > VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) > - > FixedPcdGet32 (PcdPcieBusMin) > + 1) * > SIZE_1MB; > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > index eea2d58402..9d7e2e3130 100644 > --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > @@ -46,6 +46,7 @@ > > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010 > > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011 > > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012 > + > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000013 > > # CCIX > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 > @@ -53,8 +54,8 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 > > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019 > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A > - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B > - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C > + > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001B > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001C > > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D > > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E > > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F > @@ -68,8 +69,3 @@ > > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027 > > > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029 > - > - # Remote Chip PCIe > - > gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A > - > gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B > - > gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C Isn't the remote PCIe interface more specific to the Neoverse N1 Soc ? I think we should keep the gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieXXX PCDs and remove the gArmN1SdpTokenSpaceGuid.PcdRemotePcieXXX ones instead. Also would it be possible to split the patch in 2 parts ? - CCIX root complex support enablement - other PCDs alignement Regards, Pierre -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#84925): https://edk2.groups.io/g/devel/message/84925 Mute This Topic: https://groups.io/mt/87729375/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-