Hi, > From the above point of view, your speculation is right. excellent! > In this way, if a QXL device wants to work on ARM, the io window of the > bridge it is mounted on must be allocated as 00000000-00000fff [size=4K].
That doesn't solve the cache attribute issues though ... > In my work, by modifying the qemu code, the io window of the bridge > mounted with the qxl device is fixed to 00000000-00000fff to solve > this problem. what do you think? It's not qemu but tianocore who assigns bridge windows, should be in pci scan order, i.e. lowest slot.func goes first and gets the 0000-0fff range. take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#83446): https://edk2.groups.io/g/devel/message/83446 Mute This Topic: https://groups.io/mt/86764804/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
