Hi Nate,
I will send a separate patch series that removes the v1 PPI and Protocol.
Thanks,
Michael
On 10/29/2021 6:22 PM, Nate DeSimone wrote:
Hi Michael,
Looking at your new patch series, now that we have the new PCH_SPI2_PPI, there
is no longer any need for the existence of IntelSiliconPkg/Include/Ppi/Spi.h.
The PCH_SPI_PPI will always be a silicon generation specific protocol. There is
no need to promote that protocol to the multi-generation IntelSiliconPkg.
Thanks,
Nate
-----Original Message-----
From: mikub...@linux.microsoft.com <mikub...@linux.microsoft.com>
Sent: Thursday, October 28, 2021 1:43 PM
To: devel@edk2.groups.io
Cc: Ni, Ray <ray...@intel.com>; Chaganty, Rangasai V <rangasai.v.chaga...@intel.com>;
Desimone, Nathaniel L <nathaniel.l.desim...@intel.com>
Subject: [PATCH v6 06/52] IntelSiliconPkg: Add PCH SPI PPI
From: Michael Kubacki <michael.kuba...@microsoft.com>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
This SPI PPI definition is intended to serve as the single definition for Intel
platform and silicon packages.
Cc: Ray Ni <ray...@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaga...@intel.com>
Signed-off-by: Michael Kubacki <michael.kuba...@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaga...@intel.com>
---
Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h | 25 ++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 3 +++
2 files changed, 28 insertions(+)
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h
b/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h
new file mode 100644
index 000000000000..b2410bd17300
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h
@@ -0,0 +1,25 @@
+/** @file
+ This file defines the PCH SPI PPI which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_SPI_PPI_H_ #define _PCH_SPI_PPI_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPchSpiPpiGuid;
+
+/**
+ Reuse the PCH_SPI_PROTOCOL definitions
+ This is possible becaues the PPI implementation does not rely on a
+PeiService pointer,
+ as it uses EDKII Glue Lib to do IO accesses **/ typedef
+PCH_SPI_PROTOCOL PCH_SPI_PPI;
+
+#endif
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index fb8391000347..1fa447f37722 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -71,6 +71,9 @@ [Guids]
gEdkiiMicrocodeStorageTypeFlashGuid = { 0x2cba01b3, 0xd391, 0x4598, { 0x8d,
0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd, 0x71 } }
[Ppis]
+ ## Include/Ppi/Spi.h
+ gPchSpiPpiGuid = { 0x104c7177, 0xc2e6, 0x44f0, { 0xae, 0xe3, 0x9d,
+ 0x0d, 0x9a, 0x52, 0xca, 0xdf } }
+
gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67,
0xaf, 0x2b, 0x25, 0x68, 0x4a } }
gEdkiiVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1,
0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } }
--
2.28.0.windows.1
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