This patch follows new Intel SDM to define CPUID.(EAX=7,ECX=0):EDX[30].
Signed-off-by: Star Zeng <[email protected]>
Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Cc: Ray Ni <[email protected]>
---
MdePkg/Include/Register/Intel/Cpuid.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MdePkg/Include/Register/Intel/Cpuid.h
b/MdePkg/Include/Register/Intel/Cpuid.h
index 6f77e174c115..5ec85ba561ac 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -1587,9 +1587,9 @@ typedef union {
///
UINT32 EnumeratesSupportForCapability:1;
///
- /// [Bit 30] Reserved.
+ /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.
///
- UINT32 Reserved3:1;
+ UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1;
///
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable
(SSBD).
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They
allow
--
2.27.0.windows.1
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