Create library instances of reading Machine mode timer. - MacineModeTimerLib is used to read mtime CSR through platfrom library. - EmulatedMacineModeTimerLib is used to read mtime CSR through shadow CSR.
Cc: Sunil V L <suni...@ventanamicro.com> Cc: Daniel Schaefer <daniel.schae...@hpe.com> Signed-off-by: Abner Chang <abner.ch...@hpe.com> --- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 2 + .../EmulatedMachineModeTimerLib.inf | 34 +++++++++++++++++ .../MachineModeTimerLib.inf | 38 +++++++++++++++++++ .../Include/IndustryStandard/RiscV.h | 5 +++ .../Include/Library/RiscVCpuLib.h | 3 ++ .../EmulatedMachineModeTimerLib.S | 24 ++++++++++++ .../MachineModeTimerLib/MachineModeTimerLib.S | 25 ++++++++++++ 7 files changed, 131 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc index 531319322c..3b5738957d 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc @@ -44,6 +44,8 @@ RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf + #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf new file mode 100644 index 0000000000..369028a9a6 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf @@ -0,0 +1,34 @@ +## @file +# Library to read Machine Mode Timer. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = EmulatedMachineModeTimerLib + FILE_GUID = 81B82615-D85C-4377-8BFF-7442322E2835 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MachineModeTimerLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + +[Sources.RISCV64] + EmulatedMachineModeTimerLib.S + +[Packages] + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + + + diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf new file mode 100644 index 0000000000..71d4315445 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf @@ -0,0 +1,38 @@ +## @file +# Library to read Machine Mode Timer. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = MachineModeTimerLib + FILE_GUID = 6390D8AA-E0E6-4625-A515-9BB2DC7BBCAB + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MachineModeTimerLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + +[Sources.RISCV64] + MachineModeTimerLib.S + +[Packages] + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + RiscVCpuLib + RiscVPlatformTimerLib + + + diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h index f6726bda24..c9715a2ee2 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h @@ -154,4 +154,9 @@ #define RISCV_CSR_MTOHOST 0x780 #define RISCV_CSR_MFROMHOST 0x781 +// +// User mode CSR +// +#define RISCV_CSR_CYCLE 0xc00 +#define RISCV_CSR_TIME 0xc01 #endif diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index f70723567e..8d51152fa9 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -32,6 +32,9 @@ RiscVGetMachineTrapCause (VOID); UINT64 RiscVReadMachineTimer (VOID); +UINT64 +RiscVReadMachineTimerInterface (VOID); + VOID RiscVSetMachineTimerCmp (UINT64); diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S new file mode 100644 index 0000000000..1acd0ab062 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S @@ -0,0 +1,24 @@ +//------------------------------------------------------------------------------ +// +// Read Machine mode timer using shadow CSR. +// +// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ +#include <IndustryStandard/RiscV.h> + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimerInterface) +// +// Read machine mode timer CSR through shadow CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimerInterface): + csrr a0, RISCV_CSR_TIME + ret diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S new file mode 100644 index 0000000000..16f8bdd70a --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S @@ -0,0 +1,25 @@ +//------------------------------------------------------------------------------ +// +// Read mtimer through platform library. +// +// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ +#include <RiscVImpl.h> + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimerInterface) +// +// Read machine mode timer CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimerInterface): + call RiscVReadMachineTimer + ret + -- 2.31.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82335): https://edk2.groups.io/g/devel/message/82335 Mute This Topic: https://groups.io/mt/86435688/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
