From: Abner Chang <abner.ch...@hpe.com>
Add RISC-V FirmwareContext library for different FirmwareContext
implementations. This instance uses SBI firmware extension to
get the pointer to FirmwareContext.
Cc: Sunil V L <suni...@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schae...@hpe.com>
Reviewed-by: Abner Chang <abner.ch...@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schae...@hpe.com>
Signed-off-by: Abner Chang <abner.ch...@hpe.com>
---
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
| 1 +
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
| 4 +-
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
| 34 +++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
| 33 +++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
| 34 +++++++++++++
Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
| 3 +-
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
| 14 +++++-
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
| 43 ++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
| 52 ++++++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
| 48 ++++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
| 48 ++++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
| 34 ++++++++++++-
12 files changed, 344 insertions(+), 4 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 0b64b33f0fba..08279a97b1c5 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -24,6 +24,7 @@
RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h
RiscVCpuLib|Include/Library/RiscVCpuLib.h
RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
+ RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h
[Guids]
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d,
0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 5c5cfcb525ca..1292ba1beab7 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -65,13 +65,14 @@
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
-
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
[LibraryClasses.common.PEI_CORE]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+
RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
[LibraryClasses.common.PEIM]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+
RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -92,6 +93,7 @@
[Components]
Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
diff --git
a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
new file mode 100644
index 000000000000..168b70545390
--- /dev/null
+++
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextSbiLib
+ FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVEdk2SbiLib
+
diff --git
a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
new file mode 100644
index 000000000000..750c1cf51ffa
--- /dev/null
+++
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This instance uses RISC-V Supervisor mode SCRATCH CSR
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextSscratchLib
+ FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextSscratchLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+
diff --git
a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
new file mode 100644
index 000000000000..fa894cda9164
--- /dev/null
+++
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This iinstance Supervisor mode STVEC CSR
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextStvecLib
+ FILE_GUID = 42DCFFAC-1DBD-4264-80A3-85CC7167AC82
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextStvecLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index 2a992394edbb..f6726bda240b 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -96,6 +96,7 @@
#define SSTATUS_SIE_BIT_POSITION 1
#define SSTATUS_SPP_BIT_POSITION 8
#define RISCV_CSR_SUPERVISOR_SIE 0x104
+#define RISCV_CSR_SUPERVISOR_STVEC 0x105
#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
#define RISCV_CSR_SUPERVISOR_SEPC 0x141
#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index f37d4c20d068..f70723567e22 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -1,7 +1,7 @@
/** @file
RISC-V CPU library definitions.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+ Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -68,4 +68,16 @@ RiscVReadMachineImplementId (VOID);
VOID
RiscVSetSupervisorAddressTranslationRegister(UINT64);
+VOID
+RiscVSetSupervisorScratch (UINT64);
+
+UINT64
+RiscVGetSupervisorScratch (VOID);
+
+VOID
+RiscVSetSupervisorStvec (UINT64);
+
+UINT64
+RiscVGetSupervisorStvec (VOID);
+
#endif
diff --git
a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
new file mode 100644
index 000000000000..f35c4e0c5123
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
@@ -0,0 +1,43 @@
+/** @file
+ Library to get/set Firmware Context.
+
+ Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_FIRMWARE_CONTEXT_LIB_H_
+#define RISCV_FIRMWARE_CONTEXT_LIB_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ );
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ );
+
+#endif
diff --git
a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
new file mode 100644
index 000000000000..6125618eaf4d
--- /dev/null
+++
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
@@ -0,0 +1,52 @@
+/** @file
+ This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
+ get the pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVEdk2SbiLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ SbiGetFirmwareContext (FirmwareContextPtr);
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ //
+ // We don't have to set firmware context pointer using
+ // OpenSBI FW Extension SBI.
+ //
+}
+
diff --git
a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
new file mode 100644
index 000000000000..2504e17132c4
--- /dev/null
+++
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
@@ -0,0 +1,48 @@
+/** @file
+ This instance uses Supervisor mode SCRATCH CSR to get/set the
+ pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through Supervisor mode SCRATCH CSR.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT
*)RiscVGetSupervisorScratch ();
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through Supervisor mode SCRATCH CSR.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr);
+}
diff --git
a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
new file mode 100644
index 000000000000..7d1675355a50
--- /dev/null
+++
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
@@ -0,0 +1,48 @@
+/** @file
+ This instance uses This iinstance Supervisor mode STVEC CSR to
+ get/set the pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through Supervisor mode STVEC CSR.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT
*)RiscVGetSupervisorStvec ();
+}
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through Supervisor mode STVEC CSR
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr);
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
index 06ba80cb5fcb..e242c9b866a1 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -2,7 +2,7 @@
//
// RISC-V CPU functions.
//
-// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -101,6 +101,38 @@ ASM_FUNC (RiscVReadMachineImplementId)
csrr a0, RISCV_CSR_MACHINE_MIMPID
ret
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+ csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+ csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
+ ret
+
+//
+// Set Supervisor mode trap vector.
+// @param a0 : Value set to Supervisor mode trap vector
+//
+ASM_FUNC (RiscVSetSupervisorStvec)
+ csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode trap vector
+//
+ASM_FUNC (RiscVGetSupervisorStvec)
+ csrr a0, RISCV_CSR_SUPERVISOR_STVEC
+ ret
+
//
// Set Supervisor Address Translation and
// Protection Register.
--
2.31.1
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