On Wed, Oct 13, 2021 at 11:57:08AM -0500, Brijesh Singh wrote: > From: Michael Roth <michael.r...@amd.com> > > During AP bringup, just after switching to long mode, APs will do some > cpuid calls to verify that the extended topology leaf (0xB) is available > so they can fetch their x2 APIC IDs from it. In the case of SEV-ES, > these cpuid instructions must be handled by direct use of the GHCB MSR > protocol to fetch the values from the hypervisor, since a #VC handler > is not yet available due to the AP's stack not being set up yet. > > For SEV-SNP, rather than relying on the GHCB MSR protocol, it is > expected that these values would be obtained from the SEV-SNP CPUID > table instead. The actual x2 APIC ID (and 8-bit APIC IDs) would still > be fetched from hypervisor using the GHCB MSR protocol however, so > introducing support for the SEV-SNP CPUID table in that part of the AP > bring-up code would only be to handle the checks/validation of the > extended topology leaf. > > Rather than introducing all the added complexity needed to handle these > checks via the CPUID table, instead let the BSP do the check in advance, > since it can make use of the #VC handler to avoid the need to scan the > SNP CPUID table directly, and add a flag in ExchangeInfo to communicate > the result of this check to APs.
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