Hi Nhi,
Following up with the comment I also made for 12/28:
On Wed, Sep 15, 2021 at 22:55:00 +0700, Nhi Pham wrote:
> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h
> b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h
> new file mode 100644
> index 000000000000..66286bfff145
> --- /dev/null
> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h
> @@ -0,0 +1,317 @@
> +/** @file
> +
> + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef PLATFORM_AC01_H_
> +#define PLATFORM_AC01_H_
> +
> +//
> +// Number of supported sockets in the platform
> +//
> +#define PLATFORM_CPU_MAX_SOCKET 2
> +
> +//
> +// Maximum number of CPMs in the chip.
> +//
> +#define PLATFORM_CPU_MAX_CPM (FixedPcdGet32 (PcdClusterCount))
> +
> +//
> +// Number of cores per CPM.
> +//
> +#define PLATFORM_CPU_NUM_CORES_PER_CPM (FixedPcdGet32 (PcdCoreCount) /
> PLATFORM_CPU_MAX_CPM)
> +
> +//
> +// Socket bit offset of core UID.
> +//
> +#define PLATFORM_SOCKET_UID_BIT_OFFSET 16
> +
> +//
> +// CPM bit offset of core UID.
> +//
> +#define PLATFORM_CPM_UID_BIT_OFFSET 8
> +
> +//
> +// Maximum number of cores supported.
> +//
> +#define PLATFORM_CPU_MAX_NUM_CORES (PLATFORM_CPU_MAX_SOCKET *
> PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM)
> +
> +//
> +// Maximum number of memory region
> +//
> +#define PLATFORM_DRAM_INFO_MAX_REGION 16
> +
> +//
> +// Maximum number of DDR slots supported
> +//
> +#define PLATFORM_DIMM_INFO_MAX_SLOT 32
> +
> +//
> +// Maximum number of memory supported.
> +//
> +#define PLATFORM_MAX_MEMORY_REGION 4
> +
> +//
> +// The Array of Soc Gpio Base Address
> +//
> +#define GPIO_DWAPB_BASE_ADDR 0x1000026f0000, 0x1000026e0000,
> 0x1000027b0000, 0x1000026d0000, 0x5000026f0000, 0x5000026e0000,
> 0x5000027b0000, 0x5000026d0000
Like I said in 12/28 - I'm OK with this use of lists in macros, but
all such macros must be
However, this and the subsequent macro are not used until 6/28 - so
please also move them to that patch.
Keep the R-b for both patches once you've done that, but please also
make a pass and see if there are further things defined in this patch
that are not used until later.
Best Regards,
Leif
> +
> +//
> +// The Array of Soc Gpi Base Address
> +//
> +#define GPI_DWAPB_BASE_ADDR 0x1000026d0000, 0x5000026d0000
> +
> +//
> +// Number of Pins Per Each Contoller
> +//
> +#define GPIO_DWAPB_PINS_PER_CONTROLLER 8
> +
> +//
> +// Number of Pins Each Socket
> +//
> +#define GPIO_DWAPB_PINS_PER_SOCKET 32
> +
> +//
> +// The maximum number of I2C bus
> +//
> +#define MAX_PLATFORM_I2C_BUS_NUM 2
> +
> +//
> +// The base address of DW I2C
> +//
> +#define PLATFORM_I2C_REGISTER_BASE 0x1000026B0000ULL,
> 0x100002750000ULL
> +
> +//
> +// Offset of failsafe testing feature
> +//
> +#define NV_UEFI_FAILURE_FAILSAFE_OFFSET 0x1F8
> +
> +//
> +// Maximum number of memory controller supports NVDIMM-N per socket
> +//
> +#define PLATFORM_NVDIMM_MCU_MAX_PER_SK 2
> +
> +//
> +// Maximum number of NVDIMM-N per memory controller
> +//
> +#define PLATFORM_NVDIMM_NUM_MAX_PER_MCU 1
> +
> +//
> +// Maximum number of NVDIMM region per socket
> +//
> +#define PLATFORM_NVDIMM_REGION_MAX_PER_SK 2
> +
> +//
> +// Socket 0 base address of NVDIMM non-hashed region 0
> +//
> +#define PLATFORM_NVDIMM_SK0_NHASHED_REGION0 0x0B0000000000ULL
> +
> +//
> +// Socket 0 base address of NVDIMM non-hashed region 1
> +//
> +#define PLATFORM_NVDIMM_SK0_NHASHED_REGION1 0x0F0000000000ULL
> +
> +//
> +// Socket 1 base address of NVDIMM non-hashed region 0
> +//
> +#define PLATFORM_NVDIMM_SK1_NHASHED_REGION0 0x430000000000ULL
> +
> +//
> +// Socket 1 base address of NVDIMM non-hashed region 1
> +//
> +#define PLATFORM_NVDIMM_SK1_NHASHED_REGION1 0x470000000000ULL
> +
> +//
> +// DIMM ID of NVDIMM-N device 1
> +//
> +#define PLATFORM_NVDIMM_NVD1_DIMM_ID 6
> +
> +//
> +// DIMM ID of NVDIMM-N device 2
> +//
> +#define PLATFORM_NVDIMM_NVD2_DIMM_ID 14
> +
> +//
> +// DIMM ID of NVDIMM-N device 3
> +//
> +#define PLATFORM_NVDIMM_NVD3_DIMM_ID 22
> +
> +//
> +// DIMM ID of NVDIMM-N device 4
> +//
> +#define PLATFORM_NVDIMM_NVD4_DIMM_ID 30
> +
> +//
> +// NFIT device handle of NVDIMM-N device 1
> +//
> +#define PLATFORM_NVDIMM_NVD1_DEVICE_HANDLE 0x0330
> +
> +//
> +// NFIT device handle of NVDIMM-N device 2
> +//
> +#define PLATFORM_NVDIMM_NVD2_DEVICE_HANDLE 0x0770
> +
> +//
> +// NFIT device handle of NVDIMM-N device 3
> +//
> +#define PLATFORM_NVDIMM_NVD3_DEVICE_HANDLE 0x1330
> +
> +//
> +// NFIT device handle of NVDIMM-N device 4
> +//
> +#define PLATFORM_NVDIMM_NVD4_DEVICE_HANDLE 0x1770
> +
> +//
> +// Interleave ways of non-hashed NVDIMM-N
> +//
> +#define PLATFORM_NVDIMM_NHASHED_INTERLEAVE_WAYS 1
> +
> +//
> +// Interleave ways of hashed NVDIMM-N
> +//
> +#define PLATFORM_NVDIMM_HASHED_INTERLEAVE_WAYS 2
> +
> +//
> +// Region offset of hashed NVDIMM-N
> +//
> +#define PLATFORM_NVDIMM_HASHED_REGION_OFFSET 512
> +
> +//
> +// The base address of master socket GIC redistributor registers
> +//
> +#define GICR_MASTER_BASE_REG 0x100100140000
> +
> +//
> +// The base address of GIC distributor registers
> +//
> +#define GICD_BASE_REG 0x100100000000
> +
> +//
> +// The base address of slave socket GIC redistributor registers
> +//
> +#define GICR_SLAVE_BASE_REG 0x500100140000
> +
> +//
> +// The base address of slave socket GIC distributor registers
> +//
> +#define GICD_SLAVE_BASE_REG 0x500100000000
> +
> +//
> +// CSR Address base for slave socket
> +//
> +#define SLAVE_SOCKET_BASE_ADDRESS_OFFSET 0x400000000000
> +
> +//
> +// Socket 0 first RC
> +//
> +#define SOCKET0_FIRST_RC 2
> +
> +//
> +// Socket 0 last RC
> +//
> +#define SOCKET0_LAST_RC 7
> +
> +//
> +// Socket 1 first RC
> +//
> +#define SOCKET1_FIRST_RC 10
> +
> +//
> +// Socket 1 last RC
> +//
> +#define SOCKET1_LAST_RC 15
> +
> +//
> +// SMpro EFUSE Shadow register
> +//
> +#define SMPRO_EFUSE_SHADOW0 (FixedPcdGet64 (PcdSmproEfuseShadow0))
> +
> +//
> +// 2P Configuration Register
> +//
> +#define CFG2P_OFFSET 0x200
> +
> +//
> +// Slave socket present
> +//
> +#define SLAVE_PRESENT_N BIT1
> +
> +//
> +// Max number for AC01 PCIE Root Complexes per socket
> +//
> +#define AC01_MAX_RCS_PER_SOCKET 8
> +
> +//
> +// Max number for AC01 PCIE Root Complexes
> +//
> +#define AC01_MAX_PCIE_ROOT_COMPLEX 16
> +
> +//
> +// Max number for AC01 PCIE Root Bridge under each Root Complex
> +//
> +#define AC01_MAX_PCIE_ROOT_BRIDGE 1
> +
> +//
> +// The base address of {TCU, CSR, MMCONFIG} Registers
> +//
> +#define AC01_PCIE_REGISTER_BASE 0x33FFE0000000, 0x37FFE0000000,
> 0x3BFFE0000000, 0x3FFFE0000000, 0x23FFE0000000, 0x27FFE0000000,
> 0x2BFFE0000000, 0x2FFFE0000000, 0x73FFE0000000, 0x77FFE0000000,
> 0x7BFFE0000000, 0x7FFFE0000000, 0x63FFE0000000, 0x67FFE0000000,
> 0x6BFFE0000000, 0x6FFFE0000000
> +
> +//
> +// The base address of MMIO Registers
> +//
> +#define AC01_PCIE_MMIO_BASE 0x300000000000, 0x340000000000,
> 0x380000000000, 0x3C0000000000, 0x200000000000, 0x240000000000,
> 0x280000000000, 0x2C0000000000, 0x700000000000, 0x740000000000,
> 0x780000000000, 0x7C0000000000, 0x600000000000, 0x640000000000,
> 0x680000000000, 0x6C0000000000
> +
> +//
> +// The base address of MMIO32 Registers
> +//
> +#define AC01_PCIE_MMIO32_BASE 0x000020000000, 0x000028000000,
> 0x000030000000, 0x000038000000, 0x000001000000, 0x000008000000,
> 0x000010000000, 0x000018000000, 0x000060000000, 0x000068000000,
> 0x000070000000, 0x000078000000, 0x000040000000, 0x000048000000,
> 0x000050000000, 0x000058000000
> +
> +//
> +// The base address of MMIO32 Registers
> +//
> +#define AC01_PCIE_MMIO32_BASE_1P 0x000040000000, 0x000050000000,
> 0x000060000000, 0x000070000000, 0x000001000000, 0x000010000000,
> 0x000020000000, 0x000030000000, 0, 0, 0, 0, 0, 0, 0, 0
> +
> +//
> +// DSDT RCA2 PCIe Meme32 Attribute
> +//
> +#define AC01_PCIE_RCA2_QMEM 0x0000000000000000, 0x0000000060000000,
> 0x000000006FFFFFFF, 0x0000000000000000, 0x0000000010000000
> +
> +//
> +// DSDT RCA3 PCIe Meme32 Attribute
> +//
> +#define AC01_PCIE_RCA3_QMEM 0x0000000000000000, 0x0000000070000000,
> 0x000000007FFFFFFF, 0x0000000000000000, 0x0000000010000000
> +
> +//
> +// DSDT RCB0 PCIe Meme32 Attribute
> +//
> +#define AC01_PCIE_RCB0_QMEM 0x0000000000000000, 0x0000000001000000,
> 0x000000000FFFFFFF, 0x0000000000000000, 0x000000000F000000
> +
> +//
> +// DSDT RCB1 PCIe Meme32 Attribute
> +//
> +#define AC01_PCIE_RCB1_QMEM 0x0000000000000000, 0x0000000010000000,
> 0x000000001FFFFFFF, 0x0000000000000000, 0x0000000010000000
> +
> +//
> +// DSDT RCB2 PCIe Meme32 Attribute
> +//
> +#define AC01_PCIE_RCB2_QMEM 0x0000000000000000, 0x0000000020000000,
> 0x000000002FFFFFFF, 0x0000000000000000, 0x0000000010000000
> +
> +//
> +// DSDT RCB3 PCIe Meme32 Attribute
> +//
> +#define AC01_PCIE_RCB3_QMEM 0x0000000000000000, 0x0000000030000000,
> 0x000000003FFFFFFF, 0x0000000000000000, 0x0000000010000000
> +
> +//
> +// The start of TBU PMU IRQ array.
> +//
> +#define AC01_SMMU_TBU_PMU_IRQS 224, 230, 236, 242, 160, 170, 180, 190,
> 544, 550, 556, 562, 480, 490, 500, 510
> +
> +//
> +// The start of TCU PMU IRQ array
> +//
> +#define AC01_SMMU_TCU_PMU_IRQS 256, 257, 258, 259, 260, 261, 262, 263,
> 576, 577, 578, 579, 580, 581, 582, 583
> +
> +#endif /* PLATFORM_AC01_H_ */
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