Reviewed-by: Chasel Chiu <chasel.c...@intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.o...@intel.com>
> Sent: Thursday, September 16, 2021 3:05 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desim...@intel.com>; Chiu, Chasel
> <chasel.c...@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 2/2]
> WhitleyOpenBoardPkg/SecCore: Add SecCore source code support
>
> Add PlatformSecLib
> so that we can build SecCore.
> This uses FSP TempRamInit API in dispatch mode, but directly
> tears down NEM as a workaround because the current FSP binaries
> do not properly produce the TEMP_RAM_EXIT_PPI.
>
> Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
> Cc: Chasel Chiu <chasel.c...@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.o...@intel.com>
> ---
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Fs
> pWrapperPlatformSecLib.c | 159 +++++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia
> 32/Fsp.h | 43 +++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia
> 32/PeiCoreEntry.nasm | 124 +++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia
> 32/SecEntry.nasm | 338 ++++++++++++++++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia
> 32/Stack.nasm | 71 ++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Pl
> atformInit.c | 48 +++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
> cFspWrapperPlatformSecLib.inf | 103 ++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
> cGetPerformance.c | 90 ++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
> cPlatformInformation.c | 79 +++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
> cRamInitData.c | 29 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
> cTempRamDone.c | 130 ++++++++
> Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> | 30 +-
> Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> | 30 +-
> Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> |
> 2 -
> 14 files changed, 1248 insertions(+), 28 deletions(-)
>
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> FspWrapperPlatformSecLib.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> FspWrapperPlatformSecLib.c
> new file mode 100644
> index 0000000000..5e0f2ff1ac
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> FspWrapperPlatformSecLib.c
> @@ -0,0 +1,159 @@
> +/** @file
> + Sample to provide FSP wrapper platform sec related function.
> +
> + @copyright
> + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPlatformInformation.h>
> +#include <Ppi/SecPerformance.h>
> +#include <Ppi/PeiCoreFvLocation.h>
> +
> +#include <Library/LocalApicLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +/**
> + This interface conveys state information out of the Security (SEC) phase
> into
> PEI.
> +
> + @param[in] PeiServices Pointer to the PEI Services Table.
> + @param[in,out] StructureSize Pointer to the variable
> describing size of
> the input buffer.
> + @param[out] PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecPlatformInformation (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINT64 *StructureSize,
> + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord
> + );
> +
> +/**
> + This interface conveys performance information out of the Security (SEC)
> phase into PEI.
> +
> + This service is published by the SEC phase. The SEC phase handoff has an
> optional
> + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the
> + PEI Foundation. As such, if the platform supports collecting performance
> data
> in SEC,
> + this information is encapsulated into the data structure abstracted by this
> service.
> + This information is collected for the boot-strap processor (BSP) on IA-32.
> +
> + @param[in] PeiServices The pointer to the PEI Services Table.
> + @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.
> + @param[out] Performance The pointer to performance data collected in SEC
> phase.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecGetPerformance (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_SEC_PERFORMANCE_PPI *This,
> + OUT FIRMWARE_SEC_PERFORMANCE *Performance
> + );
> +
> +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
> + SecGetPerformance
> +};
> +
> +EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
> + (VOID *) (UINTN) FixedPcdGet32 (PcdFlashFvPreMemoryBase)
> +};
> +
> +EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gEfiPeiCoreFvLocationPpiGuid,
> + &mPeiCoreFvLocationPpi
> + }
> +};
> +
> +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
> + //
> + // This must be the first PPI in the list because it will be patched in
> SecPlatformMain ();
> + //
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gTopOfTemporaryRamPpiGuid,
> + NULL
> + }
> +};
> +
> +/**
> + A developer supplied function to perform platform specific operations.
> +
> + It's a developer supplied function to perform any operations appropriate
> to a
> + given platform. It's invoked just before passing control to PEI core by SEC
> + core. Platform developer may modify the SecCoreData passed to PEI Core.
> + It returns a platform specific PPI list that platform wishes to pass to
> PEI core.
> + The Generic SEC core module will merge this list to join the final list
> passed to
> + PEI core.
> +
> + @param[in,out] SecCoreData The same parameter as passing to PEI
> core. It
> + could be overridden by this function.
> +
> + @return The platform specific PPI list to be passed to PEI core or
> + NULL if there is no need of such platform specific PPI list.
> +
> +**/
> +EFI_PEI_PPI_DESCRIPTOR *
> +EFIAPI
> +SecPlatformMain (
> + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
> + )
> +{
> + EFI_PEI_PPI_DESCRIPTOR *PpiList;
> + UINT8 TopOfTemporaryRamPpiIndex;
> + UINT8 *CopyDestinationPointer;
> + UINTN ReservedSize;
> +
> + DEBUG((DEBUG_INFO, "SecPlatformMain\n"));
> +
> + ReservedSize = ALIGN_VALUE (PcdGet32 (PcdPeiTemporaryRamRcHeapSize),
> SIZE_4KB);
> + ReservedSize += ALIGN_VALUE (PcdGet32 (PcdFspTemporaryRamSize),
> SIZE_4KB);
> +
> + SecCoreData->PeiTemporaryRamBase = (UINT8 *) SecCoreData-
> >PeiTemporaryRamBase + ReservedSize;
> + SecCoreData->PeiTemporaryRamSize -= ReservedSize;
> +
> + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n",
> SecCoreData->BootFirmwareVolumeBase));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n",
> SecCoreData->BootFirmwareVolumeSize));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n",
> SecCoreData->TemporaryRamBase));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n",
> SecCoreData->TemporaryRamSize));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n",
> SecCoreData->PeiTemporaryRamBase));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n",
> SecCoreData->PeiTemporaryRamSize));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n",
> SecCoreData->StackBase));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n",
> SecCoreData->StackSize));
> +
> + InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
> +
> + //
> + // Use middle of Heap as temp buffer, it will be copied by caller.
> + // Do not use Stack, because it will cause wrong calculation on stack by
> PeiCore
> + //
> + PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN)
> SecCoreData->PeiTemporaryRamSize/2);
> + CopyDestinationPointer = (UINT8 *) PpiList;
> + TopOfTemporaryRamPpiIndex = 0;
> + if ((PcdGet8 (PcdFspModeSelection) == 0) && PcdGetBool
> (PcdFspDispatchModeUseFspPeiMain)) {
> + //
> + // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
> + //
> + CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof
> (mPeiCoreFvLocationPpiList));
> + TopOfTemporaryRamPpiIndex = 1;
> + CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
> + }
> + CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof
> (mPeiSecPlatformPpi));
> + //
> + // Patch TopOfTemporaryRamPpi
> + //
> + PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData-
> >TemporaryRamBase + SecCoreData->TemporaryRamSize);
> +
> + return PpiList;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/Fsp.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/Fsp.h
> new file mode 100644
> index 0000000000..0a8d9bf74a
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/Fsp.h
> @@ -0,0 +1,43 @@
> +/** @file
> + Fsp related definitions
> +
> + @copyright
> + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef __FSP_H__
> +#define __FSP_H__
> +
> +//
> +// Fv Header
> +//
> +#define FVH_SIGINATURE_OFFSET 0x28
> +#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH
> +#define FVH_HEADER_LENGTH_OFFSET 0x30
> +#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
> +#define FVH_EXTHEADER_SIZE_OFFSET 0x10
> +
> +//
> +// Ffs Header
> +//
> +#define FSP_HEADER_GUID_DWORD1 0x912740BE
> +#define FSP_HEADER_GUID_DWORD2 0x47342284
> +#define FSP_HEADER_GUID_DWORD3 0xB08471B9
> +#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
> +#define FFS_HEADER_SIZE_VALUE 0x18
> +
> +//
> +// Section Header
> +//
> +#define SECTION_HEADER_TYPE_OFFSET 0x03
> +#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
> +
> +//
> +// Fsp Header
> +//
> +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
> +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
> +
> +#endif
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/PeiCoreEntry.nasm
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/PeiCoreEntry.nasm
> new file mode 100644
> index 0000000000..917411cac2
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/PeiCoreEntry.nasm
> @@ -0,0 +1,124 @@
> +;------------------------------------------------------------------------------
> +; @file PeiCoreEntry.nasm
> +; Find and call SecStartup
> +;
> +; @copyright
> +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
> +;
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;------------------------------------------------------------------------------
> +
> +SECTION .text
> +
> +extern ASM_PFX(SecStartup)
> +extern ASM_PFX(PlatformInit)
> +
> +global ASM_PFX(CallPeiCoreEntryPoint)
> +ASM_PFX(CallPeiCoreEntryPoint):
> + ;
> + ; Obtain the hob list pointer
> + ;
> + mov eax, [esp+4]
> + ;
> + ; Obtain the stack information
> + ; ECX: start of range
> + ; EDX: end of range
> + ;
> + mov ecx, [esp+8]
> + mov edx, [esp+0xC]
> +
> + ;
> + ; Platform init
> + ;
> + pushad
> + push edx
> + push ecx
> + push eax
> + call ASM_PFX(PlatformInit)
> + pop eax
> + pop eax
> + pop eax
> + popad
> +
> + ;
> + ; Set stack top pointer
> + ;
> + mov esp, edx
> +
> + ;
> + ; Push the hob list pointer
> + ;
> + push eax
> +
> + ;
> + ; Save the value
> + ; ECX: start of range
> + ; EDX: end of range
> + ;
> + mov ebp, esp
> + push ecx
> + push edx
> +
> + ;
> + ; Push processor count to stack first, then BIST status (AP then BSP)
> + ;
> + mov eax, 1
> + cpuid
> + shr ebx, 16
> + and ebx, 0xFF
> + cmp bl, 1
> + jae PushProcessorCount
> +
> + ;
> + ; Some processors report 0 logical processors. Effectively 0 = 1.
> + ; So we fix up the processor count
> + ;
> + inc ebx
> +
> +PushProcessorCount:
> + push ebx
> +
> + ;
> + ; We need to implement a long-term solution for BIST capture. For now, we
> just copy BSP BIST
> + ; for all processor threads
> + ;
> + xor ecx, ecx
> + mov cl, bl
> +PushBist:
> + movd eax, mm0
> + push eax
> + loop PushBist
> +
> + ; Save Time-Stamp Counter
> + movd eax, mm5
> + push eax
> +
> + movd eax, mm6
> + push eax
> +
> + ;
> + ; Pass entry point of the PEI core
> + ;
> + mov edi, 0xFFFFFFE0
> + push DWORD [edi]
> +
> + ;
> + ; Pass BFV into the PEI Core
> + ;
> + mov edi, 0xFFFFFFFC
> + push DWORD [edi]
> +
> + ;
> + ; Pass stack size into the PEI Core
> + ;
> + mov ecx, [ebp - 4]
> + mov edx, [ebp - 8]
> + push ecx ; RamBase
> +
> + sub edx, ecx
> + push edx ; RamSize
> +
> + ;
> + ; Pass Control into the PEI Core
> + ;
> + call ASM_PFX(SecStartup)
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/SecEntry.nasm
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/SecEntry.nasm
> new file mode 100644
> index 0000000000..091990d627
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/SecEntry.nasm
> @@ -0,0 +1,338 @@
> +;------------------------------------------------------------------------------
> +; @file SecEntry.nasm
> +; This is the code that goes from real-mode to protected mode.
> +; It consumes the reset vector, calls TempRamInit API from FSP binary.
> +;
> +; @copyright
> +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
> +;
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;------------------------------------------------------------------------------
> +
> +#include "Fsp.h"
> +
> +SECTION .text
> +
> +extern ASM_PFX(CallPeiCoreEntryPoint)
> +extern ASM_PFX(FsptUpdDataPtr)
> +extern ASM_PFX(BoardBeforeTempRamInit)
> +
> +; Pcds
> +extern ASM_PFX(PcdGet32 (PcdFlashFvFspTBase))
> +
> +;----------------------------------------------------------------------------
> +;
> +; Procedure: _ModuleEntryPoint
> +;
> +; Input: None
> +;
> +; Output: None
> +;
> +; Destroys: Assume all registers
> +;
> +; Description:
> +;
> +; Transition to non-paged flat-model protected mode from a
> +; hard-coded GDT that provides exactly two descriptors.
> +; This is a bare bones transition to protected mode only
> +; used for a while in PEI and possibly DXE.
> +;
> +; After enabling protected mode, a far jump is executed to
> +; transfer to PEI using the newly loaded GDT.
> +;
> +; Return: None
> +;
> +; MMX Usage:
> +; MM0 = BIST State
> +; MM5 = Save time-stamp counter value high32bit
> +; MM6 = Save time-stamp counter value low32bit.
> +;
> +;----------------------------------------------------------------------------
> +
> +BITS 16
> +align 4
> +global ASM_PFX(_ModuleEntryPoint)
> +ASM_PFX(_ModuleEntryPoint):
> + fninit ; clear any pending Floating point
> exceptions
> + ;
> + ; Store the BIST value in mm0
> + ;
> + movd mm0, eax
> +
> + ;
> + ; Save time-stamp counter value
> + ; rdtsc load 64bit time-stamp counter to EDX:EAX
> + ;
> + rdtsc
> + movd mm5, edx
> + movd mm6, eax
> +
> + ;
> + ; Load the GDT table in GdtDesc
> + ;
> + mov esi, GdtDesc
> + DB 66h
> + lgdt [cs:si]
> +
> + ;
> + ; Transition to 16 bit protected mode
> + ;
> + mov eax, cr0 ; Get control register 0
> + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
> + mov cr0, eax ; Activate protected mode
> +
> + mov eax, cr4 ; Get control register 4
> + or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT
> bit (bit
> #10)
> + mov cr4, eax
> +
> + ;
> + ; Now we're in 16 bit protected mode
> + ; Set up the selectors for 32 bit protected mode entry
> + ;
> + mov ax, SYS_DATA_SEL
> + mov ds, ax
> + mov es, ax
> + mov fs, ax
> + mov gs, ax
> + mov ss, ax
> +
> + ;
> + ; Transition to Flat 32 bit protected mode
> + ; The jump to a far pointer causes the transition to 32 bit mode
> + ;
> + mov esi, ProtectedModeEntryLinearAddress
> + jmp dword far [cs:si]
> +
> +;----------------------------------------------------------------------------
> +;
> +; Procedure: ProtectedModeEntryPoint
> +;
> +; Input: None
> +;
> +; Output: None
> +;
> +; Destroys: Assume all registers
> +;
> +; Description:
> +;
> +; This function handles:
> +; Call two basic APIs from FSP binary
> +; Initializes stack with some early data (BIST, PEI entry, etc)
> +;
> +; Return: None
> +;
> +;----------------------------------------------------------------------------
> +
> +BITS 32
> +align 4
> +ProtectedModeEntryPoint:
> + ;
> + ; Early board hooks
> + ;
> + mov esp, BoardBeforeTempRamInitRet
> + jmp ASM_PFX(BoardBeforeTempRamInit)
> +
> +BoardBeforeTempRamInitRet:
> +
> + ; Find the fsp info header
> + mov edi, [ASM_PFX(PcdGet32 (PcdFlashFvFspTBase))]
> +
> + mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
> + cmp eax, FVH_SIGINATURE_VALID_VALUE
> + jnz FspHeaderNotFound
> +
> + xor eax, eax
> + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
> + cmp ax, 0
> + jnz FspFvExtHeaderExist
> +
> + xor eax, eax
> + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
> + add edi, eax
> + jmp FspCheckFfsHeader
> +
> +FspFvExtHeaderExist:
> + add edi, eax
> + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
> Header
> + add edi, eax
> +
> + ; Round up to 8 byte alignment
> + mov eax, edi
> + and al, 07h
> + jz FspCheckFfsHeader
> +
> + and edi, 0FFFFFFF8h
> + add edi, 08h
> +
> +FspCheckFfsHeader:
> + ; Check the ffs guid
> + mov eax, dword [edi]
> + cmp eax, FSP_HEADER_GUID_DWORD1
> + jnz FspHeaderNotFound
> +
> + mov eax, dword [edi + 4]
> + cmp eax, FSP_HEADER_GUID_DWORD2
> + jnz FspHeaderNotFound
> +
> + mov eax, dword [edi + 8]
> + cmp eax, FSP_HEADER_GUID_DWORD3
> + jnz FspHeaderNotFound
> +
> + mov eax, dword [edi + 0Ch]
> + cmp eax, FSP_HEADER_GUID_DWORD4
> + jnz FspHeaderNotFound
> +
> + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
> +
> + ; Check the section type as raw section
> + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
> + cmp al, 019h
> + jnz FspHeaderNotFound
> +
> + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
> + jmp FspHeaderFound
> +
> +FspHeaderNotFound:
> + jmp $
> +
> +FspHeaderFound:
> + ; Get the fsp TempRamInit Api address
> + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
> + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
> +
> + ; Setup the hardcode stack
> + mov esp, TempRamInitStack
> +
> + ; Call the fsp TempRamInit Api
> + jmp eax
> +
> +TempRamInitDone:
> + cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for
> Microcode Update not found.
> + je CallSecFspInit ;If microcode not found, don't hang, but continue.
> +
> + cmp eax, 0 ;Check if EFI_SUCCESS retuned.
> + jnz FspApiFailed
> +
> + ; ECX: start of range
> + ; EDX: end of range
> +CallSecFspInit:
> + xor eax, eax
> + mov esp, edx
> +
> + ; Align the stack at DWORD
> + add esp, 3
> + and esp, 0FFFFFFFCh
> +
> + push edx
> + push ecx
> + push eax ; zero - no hob list yet
> + call ASM_PFX(CallPeiCoreEntryPoint)
> +
> +FspApiFailed:
> + jmp $
> +
> +align 10h
> +TempRamInitStack:
> + DD TempRamInitDone
> + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
> +
> +;
> +; ROM-based Global-Descriptor Table for the Tiano PEI Phase
> +;
> +align 16
> +global ASM_PFX(BootGdtTable)
> +
> +;
> +; GDT[0]: 0x00: Null entry, never used.
> +;
> +NULL_SEL EQU $ - GDT_BASE ; Selector [0]
> +GDT_BASE:
> +ASM_PFX(BootGdtTable):
> + DD 0
> + DD 0
> +;
> +; Linear data segment descriptor
> +;
> +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 092h ; present, ring 0, data, expand-up,
> writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; Linear code segment descriptor
> +;
> +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 09Bh ; present, ring 0, data, expand-up,
> not-writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; System data segment descriptor
> +;
> +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 093h ; present, ring 0, data, expand-up,
> not-writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +
> +;
> +; System code segment descriptor
> +;
> +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 09Ah ; present, ring 0, data, expand-up,
> writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; Spare segment descriptor
> +;
> +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0Eh ; Changed from F000 to E000.
> + DB 09Bh ; present, ring 0, code, expand-up,
> writable
> + DB 00h ; byte-granular, 16-bit
> + DB 0
> +;
> +; Spare segment descriptor
> +;
> +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
> + DW 0FFFFh ; limit 0xFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 093h ; present, ring 0, data, expand-up,
> not-writable
> + DB 00h ; byte-granular, 16-bit
> + DB 0
> +
> +;
> +; Spare segment descriptor
> +;
> +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
> + DW 0 ; limit 0
> + DW 0 ; base 0
> + DB 0
> + DB 0 ; present, ring 0, data, expand-up,
> writable
> + DB 0 ; page-granular, 32-bit
> + DB 0
> +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
> +
> +;
> +; GDT Descriptor
> +;
> +GdtDesc: ; GDT descriptor
> + DW GDT_SIZE - 1 ; GDT limit
> + DD GDT_BASE ; GDT base address
> +
> +
> +ProtectedModeEntryLinearAddress:
> +ProtectedModeEntryLinear:
> + DD ProtectedModeEntryPoint ; Offset of our 32 bit code
> + DW LINEAR_CODE_SEL
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/Stack.nasm
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/Stack.nasm
> new file mode 100644
> index 0000000000..80a7a67ecf
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> Ia32/Stack.nasm
> @@ -0,0 +1,71 @@
> +;------------------------------------------------------------------------------
> +; @file Stack.nasm
> +; Switch the stack from temporary memory to permenent memory.
> +;
> +; @copyright
> +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
> +;
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;------------------------------------------------------------------------------
> +
> + SECTION .text
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EFIAPI
> +; SecSwitchStack (
> +; UINT32 TemporaryMemoryBase,
> +; UINT32 PermanentMemoryBase
> +; );
> +;------------------------------------------------------------------------------
> +global ASM_PFX(SecSwitchStack)
> +ASM_PFX(SecSwitchStack):
> + ;
> + ; Save three register: eax, ebx, ecx
> + ;
> + push eax
> + push ebx
> + push ecx
> + push edx
> +
> + ;
> + ; !!CAUTION!! this function address's is pushed into stack after
> + ; migration of whole temporary memory, so need save it to permanent
> + ; memory at first!
> + ;
> +
> + mov ebx, [esp + 20] ; Save the first parameter
> + mov ecx, [esp + 24] ; Save the second parameter
> +
> + ;
> + ; Save this function's return address into permanent memory at first.
> + ; Then, Fixup the esp point to permanent memory
> + ;
> + mov eax, esp
> + sub eax, ebx
> + add eax, ecx
> + mov edx, dword [esp] ; copy pushed register's value to
> permanent
> memory
> + mov dword [eax], edx
> + mov edx, dword [esp + 4]
> + mov dword [eax + 4], edx
> + mov edx, dword [esp + 8]
> + mov dword [eax + 8], edx
> + mov edx, dword [esp + 12]
> + mov dword [eax + 12], edx
> + mov edx, dword [esp + 16] ; Update this function's return address
> into
> permanent memory
> + mov dword [eax + 16], edx
> + mov esp, eax ; From now, esp is pointed to
> permanent memory
> +
> + ;
> + ; Fixup the ebp point to permanent memory
> + ;
> + mov eax, ebp
> + sub eax, ebx
> + add eax, ecx
> + mov ebp, eax ; From now, ebp is pointed to permanent
> memory
> +
> + pop edx
> + pop ecx
> + pop ebx
> + pop eax
> + ret
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> PlatformInit.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> PlatformInit.c
> new file mode 100644
> index 0000000000..546b13f8a3
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> PlatformInit.c
> @@ -0,0 +1,48 @@
> +/** @file
> + Sample to provide platform init function.
> +
> + @copyright
> + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/SerialPortLib.h>
> +#include <Library/SecBoardInitLib.h>
> +#include <Library/TestPointCheckLib.h>
> +
> +/**
> + Platform initialization.
> +
> + @param[in] FspHobList HobList produced by FSP.
> + @param[in] StartOfRange Start of temporary RAM.
> + @param[in] EndOfRange End of temporary RAM.
> +**/
> +VOID
> +EFIAPI
> +PlatformInit (
> + IN VOID *FspHobList,
> + IN VOID *StartOfRange,
> + IN VOID *EndOfRange
> + )
> +{
> + //
> + // Platform initialization
> + // Enable Serial port here
> + //
> + if (PcdGetBool(PcdSecSerialPortDebugEnable)) {
> + SerialPortInitialize ();
> + }
> +
> + DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));
> + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
> + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
> + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
> +
> + BoardAfterTempRamInit ();
> +
> + TestPointTempMemoryFunction (StartOfRange, EndOfRange);
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecFspWrapperPlatformSecLib.inf
> new file mode 100644
> index 0000000000..37e0a5cb63
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecFspWrapperPlatformSecLib.inf
> @@ -0,0 +1,103 @@
> +## @file
> +# Provide FSP wrapper platform sec related function.
> +#
> +# @copyright
> +# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +################################################################
> ################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################
> ################
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SecFspWrapperPlatformSecLib
> + FILE_GUID = 8F1AC44A-CE7E-4E29-95BB-92E321BB1573
> + MODULE_TYPE = SEC
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformSecLib
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build
> tools.
> +#
> +# VALID_ARCHITECTURES = IA32
> +#
> +
> +################################################################
> ################
> +#
> +# Sources Section - list of files that are required for the build to succeed.
> +#
> +################################################################
> ################
> +
> +[Sources]
> + FspWrapperPlatformSecLib.c
> + SecRamInitData.c
> + SecPlatformInformation.c
> + SecGetPerformance.c
> + SecTempRamDone.c
> + PlatformInit.c
> +
> +[Sources.IA32]
> + Ia32/SecEntry.nasm
> + Ia32/PeiCoreEntry.nasm
> + Ia32/Stack.nasm
> + Ia32/Fsp.h
> +
> +################################################################
> ################
> +#
> +# Package Dependency Section - list of Package files that are required for
> +# this module.
> +#
> +################################################################
> ################
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> + IntelFsp2Pkg/IntelFsp2Pkg.dec
> + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
> + WhitleySiliconPkg/CpRcPkg.dec
> + WhitleySiliconPkg/SiliconPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhitleyFspBinPkg/WhitleyFspBinPkg.dec
> +
> +[LibraryClasses]
> + LocalApicLib
> + SerialPortLib
> + DebugLib
> + BaseMemoryLib
> + FspWrapperPlatformLib
> + FspWrapperApiLib
> + SecBoardInitLib
> + TestPointCheckLib
> + PeiServicesTablePointerLib
> +
> +[Ppis]
> + gEfiSecPlatformInformationPpiGuid ## CONSUMES
> + gPeiSecPerformancePpiGuid ## CONSUMES
> + gTopOfTemporaryRamPpiGuid ## PRODUCES
> + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
> + gPlatformInitTempRamExitPpiGuid ## CONSUMES
> +
> +[Pcd]
> + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ##
> CONSUMES
> + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
> CONSUMES
> +
> +[FixedPcd]
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ##
> CONSUMES
> + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase ##
> CONSUMES
> + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize ##
> CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ##
> CONSUMES
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecGetPerformance.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecGetPerformance.c
> new file mode 100644
> index 0000000000..977212737e
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecGetPerformance.c
> @@ -0,0 +1,90 @@
> +/** @file
> + Sample to provide SecGetPerformance function.
> +
> + @copyright
> + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPerformance.h>
> +#include <Ppi/TopOfTemporaryRam.h>
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + This interface conveys performance information out of the Security (SEC)
> phase into PEI.
> +
> + This service is published by the SEC phase. The SEC phase handoff has an
> optional
> + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the
> + PEI Foundation. As such, if the platform supports collecting performance
> data
> in SEC,
> + this information is encapsulated into the data structure abstracted by this
> service.
> + This information is collected for the boot-strap processor (BSP) on IA-32.
> +
> + @param[in] PeiServices The pointer to the PEI Services Table.
> + @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.
> + @param[out] Performance The pointer to performance data collected in SEC
> phase.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecGetPerformance (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_SEC_PERFORMANCE_PPI *This,
> + OUT FIRMWARE_SEC_PERFORMANCE *Performance
> + )
> +{
> + UINT32 Size;
> + UINT32 Count;
> + UINTN TopOfTemporaryRam;
> + UINT64 Ticker;
> + VOID *TopOfTemporaryRamPpi;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gTopOfTemporaryRamPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &TopOfTemporaryRamPpi
> + );
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> + //
> + // |--------------| <- TopOfTemporaryRam - BL
> + // | List Ptr |
> + // |--------------|
> + // | BL RAM Start |
> + // |--------------|
> + // | BL RAM End |
> + // |--------------|
> + // |Number of BSPs|
> + // |--------------|
> + // | BIST |
> + // |--------------|
> + // | .... |
> + // |--------------|
> + // | TSC[63:32] |
> + // |--------------|
> + // | TSC[31:00] |
> + // |--------------|
> + //
> + TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
> + TopOfTemporaryRam -= sizeof (UINT32) * 2;
> + Count = *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));
> + Size = Count * sizeof (UINT32);
> +
> + Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof
> (UINT32) * 2);
> + Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecPlatformInformation.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecPlatformInformation.c
> new file mode 100644
> index 0000000000..3d1b9be21c
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecPlatformInformation.c
> @@ -0,0 +1,79 @@
> +/** @file
> + Sample to provide SecPlatformInformation function.
> +
> + @copyright
> + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPlatformInformation.h>
> +#include <Ppi/TopOfTemporaryRam.h>
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + This interface conveys state information out of the Security (SEC) phase
> into
> PEI.
> +
> + @param[in] PeiServices Pointer to the PEI Services Table.
> + @param[in,out] StructureSize Pointer to the variable
> describing size of
> the input buffer.
> + @param[out] PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecPlatformInformation (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINT64 *StructureSize,
> + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord
> + )
> +{
> + UINT32 *Bist;
> + UINT32 Size;
> + UINT32 Count;
> + UINTN TopOfTemporaryRam;
> + VOID *TopOfTemporaryRamPpi;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gTopOfTemporaryRamPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &TopOfTemporaryRamPpi
> + );
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // The entries of BIST information, together with the number of them,
> + // reside in the bottom of stack, left untouched by normal stack operation.
> + // This routine copies the BIST information to the buffer pointed by
> + // PlatformInformationRecord for output.
> + //
> + TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
> + TopOfTemporaryRam -= sizeof (UINT32) * 2;
> + Count = *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)));
> + Size = Count * sizeof (IA32_HANDOFF_STATUS);
> +
> + if ((*StructureSize) < (UINT64) Size) {
> + *StructureSize = Size;
> + return EFI_BUFFER_TOO_SMALL;
> + }
> +
> + *StructureSize = Size;
> + Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
> +
> + CopyMem (PlatformInformationRecord, Bist, Size);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecRamInitData.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecRamInitData.c
> new file mode 100644
> index 0000000000..a6c7a53d33
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecRamInitData.c
> @@ -0,0 +1,29 @@
> +/** @file
> + Sample to provide TempRamInitParams data.
> +
> + @copyright
> + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Library/PcdLib.h>
> +#include <FspEas.h>
> +#include <FsptUpd.h>
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr = {
> + {
> + FSPT_UPD_SIGNATURE,
> + 0x00,
> + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> + }
> + },
> + {
> + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32
> (PcdMicrocodeOffsetInFv),
> + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32
> (PcdMicrocodeOffsetInFv),
> + FixedPcdGet32 (PcdFlashSecCacheRegionBase),
> + FixedPcdGet32 (PcdFlashSecCacheRegionSize),
> + }
> +};
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecTempRamDone.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecTempRamDone.c
> new file mode 100644
> index 0000000000..e6f2c1c4d6
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
> SecTempRamDone.c
> @@ -0,0 +1,130 @@
> +/** @file
> + Sample to provide SecTemporaryRamDone function.
> +
> + @copyright
> + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/TemporaryRamDone.h>
> +#include <Ppi/PlatformInitTempRamExitPpi.h>
> +
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/FspWrapperPlatformLib.h>
> +#include <Library/FspWrapperApiLib.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +
> +#include <Guid/FspHeaderFile.h>
> +
> +#include <Register/ArchitecturalMsr.h>
> +
> +#define MSR_NEM 0x000002E0
> +
> +/**
> +This interface disables temporary memory in SEC Phase.
> +This is for dispatch mode use. We should properly produce the
> FSP_TEMP_RAM_EXIT_PPI and then call
> +that instead, but the FSP does not produce that PPI
> +**/
> +VOID
> +EFIAPI
> +SecPlatformDisableTemporaryMemoryDispatchHack (
> + VOID
> + )
> +{
> + UINT64 MsrValue;
> + UINT64 MtrrDefaultType;
> + MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
> +
> + //
> + // Force and INVD.
> + //
> + AsmInvd ();
> +
> + //
> + // Disable MTRRs.
> + //
> + DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
> + MtrrDefaultType = DefType.Uint64;
> + DefType.Bits.E = 0;
> + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
> +
> + //
> + // Force and INVD to prevent MCA error.
> + //
> + AsmInvd ();
> +
> + //
> + // Clear NEM Run and NEM Setup bits individually.
> + //
> + MsrValue = AsmReadMsr64 (MSR_NEM);
> + MsrValue &= ~((UINT64) BIT1);
> + AsmWriteMsr64 (MSR_NEM, MsrValue);
> + MsrValue &= ~((UINT64) BIT0);
> + AsmWriteMsr64 (MSR_NEM, MsrValue);
> +
> + //
> + // Restore MTRR default setting
> + //
> + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrDefaultType);
> +}
> +
> +/**
> +This interface disables temporary memory in SEC Phase.
> +**/
> +VOID
> +EFIAPI
> +SecPlatformDisableTemporaryMemory (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + VOID *TempRamExitParam;
> + CONST EFI_PEI_SERVICES **PeiServices;
> + PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;
> +
> + DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
> + PeiServices = GetPeiServicesTablePointer ();
> + ASSERT (PeiServices != NULL);
> + if (PeiServices == NULL) {
> + return ;
> + }
> + ASSERT ((*PeiServices) != NULL);
> + if ((*PeiServices) == NULL) {
> + return;
> + }
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gPlatformInitTempRamExitPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &PlatformInitTempRamExitPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> +
> + Status = PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();
> + ASSERT_EFI_ERROR (Status);
> +
> + if (PcdGet8 (PcdFspModeSelection) == 1) {
> + //
> + // FSP API mode
> + //
> + TempRamExitParam = UpdateTempRamExitParam ();
> + Status = CallTempRamExit (TempRamExitParam);
> + DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
> + ASSERT_EFI_ERROR (Status);
> + } else {
> + SecPlatformDisableTemporaryMemoryDispatchHack ();
> + }
> +
> + Status = PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();
> + ASSERT_EFI_ERROR(Status);
> +
> + return ;
> +}
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> index fa41ae923d..dc3dd0e026 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> @@ -48,6 +48,9 @@
> #
> !include $(SILICON_PKG)/MrcCommonConfig.dsc
>
> +[Packages]
> + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
> +
> !include $(FSP_BIN_PKG)/DynamicExPcd.dsc
> !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc
> !include $(RP_PKG)/DynamicExPcd.dsc
> @@ -192,8 +195,17 @@
> gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000
> gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000
>
> + #
> + # Mode | FSP_MODE | PcdFspModeSelection
> + # ------------------|----------|--------------------
> + # FSP Dispatch Mode | 1 | 0
> + # FSP API Mode | 0 | 1
> + #
> !if ($(FSP_MODE) == 0)
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
> gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000
> +!else
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
> !endif
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
>
> @@ -310,6 +322,12 @@
> !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc
>
> [PcdsFixedAtBuild.IA32]
> + #
> + # FSP Base address PCD will be updated in FDF basing on flash map.
> + #
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
> +
> !if ($(FSP_MODE) == 0)
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
> gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000
> @@ -543,12 +561,11 @@
> VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
>
> [LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE,
> LibraryClasses.Common.PEIM]
> -!if ($(FSP_MODE) == 0)
>
> FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs
> pWrapperApiLib.inf
>
> FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/
> PeiFspWrapperApiTestLib.inf
>
> FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/Fsp
> WrapperPlatformLib.inf
>
> FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobPr
> ocessLib/PeiFspWrapperHobProcessLib.inf
> -!endif
> +
>
> FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchS
> tackLib.inf
>
> FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.i
> nf
>
> FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.in
> f
> @@ -559,6 +576,11 @@
> #
>
> TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat
> e.inf
>
> +
> PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapp
> erPlatformSecLib.inf
> +
> SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecB
> oardInitLibNull.inf
> +
> TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestPoi
> ntCheckLib.inf
> +
> VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariabl
> eReadLibNull.inf
> +
> [LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
> #
> # ToDo: Can we remove
> @@ -617,6 +639,8 @@
>
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
>
> [Components.IA32]
> + UefiCpuPkg/SecCore/SecCore.inf
> +
> !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
>
> MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> @@ -653,8 +677,8 @@
>
> BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/BoardInit
> LibNull.inf
> }
>
> -!if ($(FSP_MODE) == 0)
> IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
> +!if ($(FSP_MODE) == 0)
> IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
> $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
> !endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> index 927db9e210..d128f61b9d 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> @@ -14,7 +14,7 @@ DEFINE PLATFORM_PKG = MinPlatformPkg
> # 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof
> (EFI_FFS_FILE_HEADER))
> DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
>
> -DEFINE MICROCODE_HEADER_SIZE = 0x00000090
> +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90
> # FV Header plus FFS header
>
> DEFINE VPD_HEADER_SIZE = 0x00000090
>
> @@ -153,24 +153,12 @@ SET
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
> SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
> SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
>
> - #
> - # For FSP Dispatch Mode, specify the FV containing the PEI core.
> - #
> - !if $(FSP_MODE) == 1
> - #
> - # Tell SEC to use PEI Core from outside FSP for additional debug message
> control.
> - #
> - SET gSiPkgTokenSpaceGuid.PcdPeiCoreFv =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
> - !endif
> -
> #
> # For API mode, wrappers have some duplicate PCD as well
> #
> - !if $(FSP_MODE) == 0
> - SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
> - SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
> - SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
> - !endif
> + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
> + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
> + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
>
>
> #################################################################
> ###############
> #
> @@ -311,7 +299,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
> = 0x01000000
> #
> # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> dynamically
> #
> - SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset +
> $(MICROCODE_HEADER_SIZE)
> + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset +
> gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
> + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize -
> gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
>
> #
> # FV Layout (You should not need to modify this section)
> @@ -410,12 +399,7 @@ SET
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
> !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
> FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
>
> - FILE SEC = 1BA0062E-C779-4582-8566-336AE8F78F09 {
> - SECTION UI = "SecCore"
> - SECTION VERSION = "1.0"
> - SECTION Align = 16 PE32 =
> $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/1BA0062E-C779-4582-8566-
> 336AE8F78F09SecCore.efi
> - SECTION Align = 16 RAW =
> $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ResetVec.bin
> - }
> + INF UefiCpuPkg/SecCore/SecCore.inf
> INF MdeModulePkg/Core/Pei/PeiMain.inf
>
> INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> index d7039f65c4..ea8fd0a49b 100644
> --- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> @@ -905,8 +905,6 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e,
> 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
> gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlSupported
> |FALSE|BOOLEAN|0xF0000030
> gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlEnableDefault
> |FALSE|BOOLEAN|0xF0000031
>
> - gSiPkgTokenSpaceGuid.PcdPeiCoreFv
> |0x00000000|UINT32|0xF0000032
> -
> gSiPkgTokenSpaceGuid.ReservedN|TRUE|BOOLEAN|0xF0000033
>
> #
> --
> 2.27.0.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#80835): https://edk2.groups.io/g/devel/message/80835
Mute This Topic: https://groups.io/mt/85635752/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
