The CM4 has an actual PCIe slot, so the device filtering
need to be a little less restrictive WRT busses with more
than 1 device given that switches can now appear in the
topology. Since it is possible to start numbering the
busses with a non-zero value, the bus restriction should
be based on the secondary side of the root port. This
isn't likely but its better than hard-coding the limit.
Suggested-by: René Treffer <treffer+groups...@measite.de>
Signed-off-by: Jeremy Linton <jeremy.lin...@arm.com>
---
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..6d15e82fa2 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -19,6 +19,7 @@
#include <Library/PciSegmentLib.h>
#include <Library/UefiLib.h>
#include <IndustryStandard/Bcm2711.h>
+#include <IndustryStandard/Pci30.h>
typedef enum {
PciCfgWidthUint8 = 0,
@@ -78,6 +79,9 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;
+ UINT32 HostPortSec;
Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +93,20 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+ HostPortSec = MmioRead8 (PCIE_REG_BASE +
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+
/*
- * Scan things out directly rather than translating the "bus" to a
device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus <= HostPortSec)) {
return 0xFFFFFFFF;
}
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7
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