This patch adds ACPI tables description for the SolidRun CN913x CEx7 Evaluation Board platform.
Signed-off-by: Marcin Wojtas <m...@semihalf.com> --- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf | 61 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h | 9 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h | 114 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl | 383 +++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl | 493 +++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl | 515 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl | 120 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc | 74 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc | 87 ++++ 9 files changed, 1856 insertions(+) create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf new file mode 100644 index 0000000000..27e7294014 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf @@ -0,0 +1,61 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR> +# Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR> +# Copyright (c) 2021, Semihalf.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = PlatformAcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl + Cn913xCEx7Eval/Cn9130EvalSsdt.asl + Cn913xCEx7Eval/Cn9131EvalSsdt.asl + Cn913xCEx7Eval/Cn9132EvalSsdt.asl + Cn913xCEx7Eval/Dbg2.aslc + Cn913xCEx7Eval/Mcfg.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + +[BuildOptions] + *_*_*_ASLCC_FLAGS = -DCN9131 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h new file mode 100644 index 0000000000..a18b7c1396 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h @@ -0,0 +1,9 @@ +/** + + Copyright (C) 2021, Semihalf. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define CN913X_DBG2_UART_REG_BASE 0xF2702200 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h new file mode 100644 index 0000000000..592e47d0c4 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h @@ -0,0 +1,114 @@ +/** + + Copyright (C) 2019, Marvell International Ltd. and its affiliates. + Copyright (C) 2021, Semihalf. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define CP0_PCI0_BUS_MIN 0x0 +#define CP0_PCI0_BUS_MAX 0x0 +#define CP0_PCI0_BUS_COUNT 0x1 +#define CP0_PCI0_MMIO32_BASE 0xC0000000 +#define CP0_PCI0_MMIO32_SIZE 0x20000000 +#define CP0_PCI0_MMIO32_MAX 0xDFFFFFFF +#define CP0_PCI0_MMIO64_BASE 0x810000000 +#define CP0_PCI0_MMIO64_SIZE 0x80000000 +#define CP0_PCI0_MMIO64_MAX 0x88FFFFFFF +#define CP0_PCI0_IO_BASE 0x0 +#define CP0_PCI0_IO_SIZE 0x10000 +#define CP0_PCI0_IO_TRANSLATION 0x80FF00000 +#define CP0_PCI0_ECAM_BASE 0x800008000 +#define CP0_PCI0_ECAM_SIZE 0x100000 +#define CP0_PCI0_ECAM_MAX 0x800107FFF + +#define CP1_PCI0_BUS_MIN 0x0 +#define CP1_PCI0_BUS_MAX 0x0 +#define CP1_PCI0_BUS_COUNT 0x1 +#define CP1_PCI0_MMIO32_BASE 0xE3000000 +#define CP1_PCI0_MMIO32_SIZE 0x1000000 +#define CP1_PCI0_MMIO32_MAX 0xE3FFFFFF +#define CP1_PCI0_MMIO64_BASE 0x890000000 +#define CP1_PCI0_MMIO64_SIZE 0x10000000 +#define CP1_PCI0_MMIO64_MAX 0x89FFFFFFF +#define CP1_PCI0_IO_BASE 0x0 +#define CP1_PCI0_IO_SIZE 0x10000 +#define CP1_PCI0_IO_TRANSLATION 0xE2F00000 +#define CP1_PCI0_ECAM_BASE 0xE2008000 +#define CP1_PCI0_ECAM_SIZE 0x100000 + +#define CP1_PCI1_BUS_MIN 0x0 +#define CP1_PCI1_BUS_MAX 0x0 +#define CP1_PCI1_BUS_COUNT 0x1 +#define CP1_PCI1_MMIO32_BASE 0xE5000000 +#define CP1_PCI1_MMIO32_SIZE 0x1000000 +#define CP1_PCI1_MMIO32_MAX 0xE5FFFFFF +#define CP1_PCI1_MMIO64_BASE 0x8A0000000 +#define CP1_PCI1_MMIO64_SIZE 0x10000000 +#define CP1_PCI1_MMIO64_MAX 0x8AFFFFFFF +#define CP1_PCI1_IO_BASE 0x0 +#define CP1_PCI1_IO_SIZE 0x10000 +#define CP1_PCI1_IO_TRANSLATION 0xE4F00000 +#define CP1_PCI1_ECAM_BASE 0xE4008000 +#define CP1_PCI1_ECAM_SIZE 0x100000 + +#define CP1_PCI2_BUS_MIN 0x0 +#define CP1_PCI2_BUS_MAX 0x0 +#define CP1_PCI2_BUS_COUNT 0x1 +#define CP1_PCI2_MMIO32_BASE 0xE7000000 +#define CP1_PCI2_MMIO32_SIZE 0x1000000 +#define CP1_PCI2_MMIO32_MAX 0xE7FFFFFF +#define CP1_PCI2_MMIO64_BASE 0x8B0000000 +#define CP1_PCI2_MMIO64_SIZE 0x10000000 +#define CP1_PCI2_MMIO64_MAX 0x8BFFFFFFF +#define CP1_PCI2_IO_BASE 0x0 +#define CP1_PCI2_IO_SIZE 0x10000 +#define CP1_PCI2_IO_TRANSLATION 0xE6F00000 +#define CP1_PCI2_ECAM_BASE 0xE6008000 +#define CP1_PCI2_ECAM_SIZE 0x100000 + +#define CP2_PCI0_BUS_MIN 0x0 +#define CP2_PCI0_BUS_MAX 0x0 +#define CP2_PCI0_BUS_COUNT 0x1 +#define CP2_PCI0_MMIO32_BASE 0xEA000000 +#define CP2_PCI0_MMIO32_SIZE 0x1000000 +#define CP2_PCI0_MMIO32_MAX 0xEAFFFFFF +#define CP2_PCI0_MMIO64_BASE 0x8C0000000 +#define CP2_PCI0_MMIO64_SIZE 0x10000000 +#define CP2_PCI0_MMIO64_MAX 0x8CFFFFFFF +#define CP2_PCI0_IO_BASE 0x0 +#define CP2_PCI0_IO_SIZE 0x10000 +#define CP2_PCI0_IO_TRANSLATION 0xE9F00000 +#define CP2_PCI0_ECAM_BASE 0xE9008000 +#define CP2_PCI0_ECAM_SIZE 0x100000 + +#define CP2_PCI1_BUS_MIN 0x0 +#define CP2_PCI1_BUS_MAX 0x0 +#define CP2_PCI1_BUS_COUNT 0x1 +#define CP2_PCI1_MMIO32_BASE 0xEC000000 +#define CP2_PCI1_MMIO32_SIZE 0x1000000 +#define CP2_PCI1_MMIO32_MAX 0xECFFFFFF +#define CP2_PCI1_MMIO64_BASE 0x8D0000000 +#define CP2_PCI1_MMIO64_SIZE 0x10000000 +#define CP2_PCI1_MMIO64_MAX 0x8DFFFFFFF +#define CP2_PCI1_IO_BASE 0x0 +#define CP2_PCI1_IO_SIZE 0x10000 +#define CP2_PCI1_IO_TRANSLATION 0xEBF00000 +#define CP2_PCI1_ECAM_BASE 0xEB008000 +#define CP2_PCI1_ECAM_SIZE 0x100000 + +#define CP2_PCI2_BUS_MIN 0x0 +#define CP2_PCI2_BUS_MAX 0x0 +#define CP2_PCI2_BUS_COUNT 0x1 +#define CP2_PCI2_MMIO32_BASE 0xEE000000 +#define CP2_PCI2_MMIO32_SIZE 0x1000000 +#define CP2_PCI2_MMIO32_MAX 0xEEFFFFFF +#define CP2_PCI2_MMIO64_BASE 0x8E0000000 +#define CP2_PCI2_MMIO64_SIZE 0x10000000 +#define CP2_PCI2_MMIO64_MAX 0x8EFFFFFFF +#define CP2_PCI2_IO_BASE 0x0 +#define CP2_PCI2_IO_SIZE 0x10000 +#define CP2_PCI2_IO_TRANSLATION 0xEDF00000 +#define CP2_PCI2_ECAM_BASE 0xED008000 +#define CP2_PCI2_ECAM_SIZE 0x100000 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl new file mode 100644 index 0000000000..70bdecb620 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl @@ -0,0 +1,383 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR> + Copyright (C) 2021, Semihalf.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Cn913xCEx7Eval/Dbg2.h" +#include "Cn913xCEx7Eval/Pcie.h" +#include "IcuInterrupts.h" + +DefinitionBlock ("Cn9130CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3) +{ + Scope (_SB) + { + Device (MMC1) + { + Name (_HID, "MRVL0004") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF2780000, // Address Base (MMIO) + 0x00000300, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_SDMMC + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 400000000 }, + Package () { "bus-width", 4 }, + Package () { "no-1-8-v", 0x1 }, + Package () { "broken-cd", 0x1 }, + } + }) + } + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF2500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_USB_H0 + } + }) + } + + Device (XHC1) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF2510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_USB_H1 + } + }) + } + + Device (COM2) + { + Name (_HID, "MRVL0001") // _HID: Hardware ID + Name (_CID, "HISI0031") // _CID: Compatible ID + Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: Address + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + CN913X_DBG2_UART_REG_BASE, // Address Base + 0x00000100, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_UART2 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + + Device (SMI0) + { + Name (_HID, "MRVL0100") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xf212a200, // Address Base + 0x00000010, // Address Length + ) + }) + Device (PHY0) + { + Name (_ADR, 0x0) + } + } + + Device (PP20) + { + Name (_HID, "MRVL0110") // _HID: Hardware ID + Name (_CCA, 0x01) // Cache-coherent controller + Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) + Memory32Fixed (ReadWrite, 0xf2220000 , 0x800) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + Package () { "managed", "in-band-status"}, + } + }) + } + Device (ETH1) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 1 }, + Package () { "gop-port-id", 2 }, + Package () { "phy-mode", "rgmii-id"}, + Package () { "phy-handle", \_SB.SMI0.PHY0}, + } + }) + } + Device (ETH2) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT2 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 2 }, + Package () { "gop-port-id", 3 }, + Package () { "phy-mode", "2500base-x"}, + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () {"fixed-link", "LNK0"} + } + }) + Name (LNK0, Package(){ // Data-only subnode of port + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"speed", 2500}, + Package () {"full-duplex", 1} + } + }) + } + } + + Device (RNG0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP0_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip76" }, + } + }) + } + + // + // PCIe Root Bus + // + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + CP0_PCI0_BUS_MIN, // Range Minimum + CP0_PCI0_BUS_MAX, // Range Maximum + 0x0000, // Translation Offset + CP0_PCI0_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + CP0_PCI0_MMIO32_BASE, // Range Minimum + CP0_PCI0_MMIO32_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP0_PCI0_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + CP0_PCI0_MMIO64_BASE, // Range Minimum + CP0_PCI0_MMIO64_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP0_PCI0_MMIO64_SIZE // Length + ) + QWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + CP0_PCI0_IO_BASE, // Range Minimum + 0x0000FFFF, // Range Maximum + CP0_PCI0_IO_TRANSLATION, // Translation Address + CP0_PCI0_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + CP0_PCI0_ECAM_BASE, // Range Minimum + CP0_PCI0_ECAM_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP0_PCI0_ECAM_SIZE // Length + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + } +} diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl new file mode 100644 index 0000000000..930134b86f --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl @@ -0,0 +1,493 @@ +/** @file + + Secondary System Description Table Fields (SSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR> + Copyright (C) 2021, Semihalf.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Cn913xCEx7Eval/Pcie.h" +#include "IcuInterrupts.h" + +DefinitionBlock ("Cn9131CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3) +{ + Scope (_SB) + { + Device (AHC0) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF4540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP1_SATA_H0 + } + }) + } + + Device (XHC2) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF4510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP1_USB_H1 + } + }) + } + + Device (XSM1) + { + Name (_HID, "MRVL0101") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xf412a600, // Address Base + 0x00000010, // Address Length + ) + }) + Device (PHY0) + { + Name (_ADR, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "ethernet-phy-ieee802.3-c45" }, + } + }) + } + } + + Device (PP21) + { + Name (_HID, "MRVL0110") // _HID: Hardware ID + Name (_CCA, 0x01) // Cache-coherent controller + Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000) + Memory32Fixed (ReadWrite, 0xf4220000 , 0x800) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "5gbase-r"}, + Package () { "phy-handle", \_SB.XSM1.PHY0}, + } + }) + } + } + + Device (RNG1) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP1_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip76" }, + } + }) + } + + Device (PCI1) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x01) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + CP1_PCI0_BUS_MIN, // Range Minimum + CP1_PCI0_BUS_MAX, // Range Maximum + 0x0000, // Translation Offset + CP1_PCI0_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + CP1_PCI0_MMIO32_BASE, // Range Minimum + CP1_PCI0_MMIO32_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP1_PCI0_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + CP1_PCI0_MMIO64_BASE, // Range Minimum + CP1_PCI0_MMIO64_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP1_PCI0_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + CP1_PCI0_IO_BASE, // Range Minimum + 0x0000FFFF, // Range Maximum + CP1_PCI0_IO_TRANSLATION, // Translation Address + CP1_PCI0_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI1._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + CP1_PCI0_ECAM_BASE, // Range Minimum + CP1_PCI0_ECAM_SIZE // Length + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI1.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI1.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI1.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI1.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI1._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI1._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI1._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI1._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + + Device (PCI2) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x02) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + CP1_PCI1_BUS_MIN, // Range Minimum + CP1_PCI1_BUS_MAX, // Range Maximum + 0x0000, // Translation Offset + CP1_PCI1_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + CP1_PCI1_MMIO32_BASE, // Range Minimum + CP1_PCI1_MMIO32_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP1_PCI1_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + CP1_PCI1_MMIO64_BASE, // Range Minimum + CP1_PCI1_MMIO64_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP1_PCI1_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + CP1_PCI1_IO_BASE, // Range Minimum + 0x0000FFFF, // Range Maximum + CP1_PCI1_IO_TRANSLATION, // Translation Address + CP1_PCI1_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI2._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + CP1_PCI1_ECAM_BASE, // Range Minimum + CP1_PCI1_ECAM_SIZE // Length + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI2.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI2.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI2.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI2.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI2._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI2._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI2._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI2._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + + Device (PCI3) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x03) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + CP1_PCI2_BUS_MIN, // Range Minimum + CP1_PCI2_BUS_MAX, // Range Maximum + 0x0000, // Translation Offset + CP1_PCI2_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + CP1_PCI2_MMIO32_BASE, // Range Minimum + CP1_PCI2_MMIO32_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP1_PCI2_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + CP1_PCI2_MMIO64_BASE, // Range Minimum + CP1_PCI2_MMIO64_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP1_PCI2_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + CP1_PCI2_IO_BASE, // Range Minimum + 0x0000FFFF, // Range Maximum + CP1_PCI2_IO_TRANSLATION, // Translation Address + CP1_PCI2_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI3._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + CP1_PCI2_ECAM_BASE, // Range Minimum + CP1_PCI2_ECAM_SIZE // Length + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI3.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI3.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI3.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI3.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI3._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI3._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI3._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI3._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + } +} diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl new file mode 100644 index 0000000000..64341095b1 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl @@ -0,0 +1,515 @@ +/** @file + + Secondary System Description Table Fields (SSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR> + Copyright (C) 2021, Semihalf.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Cn913xCEx7Eval/Pcie.h" +#include "IcuInterrupts.h" + +DefinitionBlock ("Cn9132CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3) +{ + Scope (_SB) + { + Device (AHC1) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF6540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP2_SATA_H0 + } + }) + } + + Device (XHC3) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF6500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP2_USB_H0 + } + }) + } + Device (XHC4) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF6510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP2_USB_H1 + } + }) + } + + Device (XSM2) + { + Name (_HID, "MRVL0101") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xf412a600, // Address Base + 0x00000010, // Address Length + ) + }) + Device (PHY0) + { + Name (_ADR, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "ethernet-phy-ieee802.3-c45" }, + } + }) + } + } + + Device (PP22) + { + Name (_HID, "MRVL0110") // _HID: Hardware ID + Name (_CCA, 0x01) // Cache-coherent controller + Name (_UID, 0x02) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf6000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf6129000 , 0xb000) + Memory32Fixed (ReadWrite, 0xf6220000 , 0x800) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP2_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "5gbase-r"}, + Package () { "phy-handle", \_SB.XSM2.PHY0}, + } + }) + } + } + + Device (RNG2) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF6760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP2_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip76" }, + } + }) + } + + Device (PCI4) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x04) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + CP2_PCI0_BUS_MIN, // Range Minimum + CP2_PCI0_BUS_MAX, // Range Maximum + 0x0000, // Translation Offset + CP2_PCI0_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + CP2_PCI0_MMIO32_BASE, // Range Minimum + CP2_PCI0_MMIO32_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP2_PCI0_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + CP2_PCI0_MMIO64_BASE, // Range Minimum + CP2_PCI0_MMIO64_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP2_PCI0_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + CP2_PCI0_IO_BASE, // Range Minimum + 0x0000FFFF, // Range Maximum + CP2_PCI0_IO_TRANSLATION, // Translation Address + CP2_PCI0_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI4._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + CP2_PCI0_ECAM_BASE, // Range Minimum + CP2_PCI0_ECAM_SIZE // Length + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI4.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI4.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI4.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI4.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI4._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI4._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI4._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI4._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + + Device (PCI5) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x05) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + CP2_PCI1_BUS_MIN, // Range Minimum + CP2_PCI1_BUS_MAX, // Range Maximum + 0x0000, // Translation Offset + CP2_PCI1_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + CP2_PCI1_MMIO32_BASE, // Range Minimum + CP2_PCI1_MMIO32_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP2_PCI1_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + CP2_PCI1_MMIO64_BASE, // Range Minimum + CP2_PCI1_MMIO64_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP2_PCI1_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + CP2_PCI1_IO_BASE, // Range Minimum + 0x0000FFFF, // Range Maximum + CP2_PCI1_IO_TRANSLATION, // Translation Address + CP2_PCI1_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI5._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + CP2_PCI1_ECAM_BASE, // Range Minimum + CP2_PCI1_ECAM_SIZE // Length + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI5.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI5.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI5.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI5.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI5._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI5._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI5._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI5._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + + Device (PCI6) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x06) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + CP2_PCI2_BUS_MIN, // Range Minimum + CP2_PCI2_BUS_MAX, // Range Maximum + 0x0000, // Translation Offset + CP2_PCI2_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + CP2_PCI2_MMIO32_BASE, // Range Minimum + CP2_PCI2_MMIO32_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP2_PCI2_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + CP2_PCI2_MMIO64_BASE, // Range Minimum + CP2_PCI2_MMIO64_MAX, // Range Maximum + 0x00000000, // Translation Offset + CP2_PCI2_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + CP2_PCI2_IO_BASE, // Range Minimum + 0x0000FFFF, // Range Maximum + CP2_PCI2_IO_TRANSLATION, // Translation Address + CP2_PCI2_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI6._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + CP2_PCI2_ECAM_BASE, // Range Minimum + CP2_PCI2_ECAM_SIZE // Length + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI6.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI6.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI6.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI6.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI6._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI6._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI6._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI6._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + } +} diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl new file mode 100644 index 0000000000..c54937fc7b --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl @@ -0,0 +1,120 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR> + Copyright (C) 2021, Semihalf.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock ("Cn913xCEx7.aml", "DSDT", 2, "MRVL", "CN9130", 3) +{ + Scope (_SB) + { + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + } + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + } + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + } + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + } + + Device (MMC0) + { + Name (_HID, "MRVL0003") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF06E0000, // Address Base (MMIO) + 0x00000300, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 48 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 400000000 }, + Package () { "bus-width", 8 }, + Package () { "no-sd", 0x1 }, + Package () { "no-sdio", 0x1 }, + Package () { "mmc-ddr-1_8v", 0x1 }, + Package () { "mmc-hs400-1_8v", 0x1 }, + Package () { "non-removable", 0x1 }, + } + }) + } + + Device (COM1) + { + Name (_HID, "MRVL0001") // _HID: Hardware ID + Name (_CID, "HISI0031") // _CID: Compatible ID + Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + FixedPcdGet64(PcdSerialRegisterBase), // Address Base + 0x00000100, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 51 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + } +} diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc new file mode 100644 index 0000000000..143da73f5c --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc @@ -0,0 +1,74 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* Copyright (c) 2021 ARM Ltd. All rights reserved. +* Copyright (c) 2021 Semihalf. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/DebugPort2Table.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> + +#include "AcpiHeader.h" +#include "Cn913xCEx7Eval/Dbg2.h" + +#pragma pack(1) + +#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 = { + { + __ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegisters */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC, + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */ + SIZE_4KB, /* AddressSize */ + CN913X_UART_STR, /* NameSpaceString */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc new file mode 100644 index 0000000000..181bbe5530 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc @@ -0,0 +1,87 @@ +/** @file + + Memory mapped config space base address table (MCFG) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR> + Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR> + Copyright (C) 2021, Semihalf.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Library/AcpiLib.h> + +#include "AcpiHeader.h" +#include "Cn913xCEx7Eval/Pcie.h" + +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h> + +#pragma pack(1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[7]; +} ACPI_6_0_MCFG_STRUCTURE; +#pragma pack() + +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg = { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MCFG_STRUCTURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), + EFI_ACPI_RESERVED_QWORD + }, + { + { + CP0_PCI0_ECAM_BASE, // BaseAddress + 0, // PciSegmentGroupNumber + CP0_PCI0_BUS_MIN, // StartBusNumber + CP0_PCI0_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + }, + { + CP1_PCI0_ECAM_BASE, // BaseAddress + 1, // PciSegmentGroupNumber + CP1_PCI0_BUS_MIN, // StartBusNumber + CP1_PCI0_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + }, + { + CP1_PCI1_ECAM_BASE, // BaseAddress + 2, // PciSegmentGroupNumber + CP1_PCI1_BUS_MIN, // StartBusNumber + CP1_PCI1_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + }, + { + CP1_PCI2_ECAM_BASE, // BaseAddress + 3, // PciSegmentGroupNumber + CP1_PCI2_BUS_MIN, // StartBusNumber + CP1_PCI2_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + }, + { + CP2_PCI0_ECAM_BASE, // BaseAddress + 4, // PciSegmentGroupNumber + CP2_PCI0_BUS_MIN, // StartBusNumber + CP2_PCI0_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + }, + { + CP2_PCI1_ECAM_BASE, // BaseAddress + 5, // PciSegmentGroupNumber + CP2_PCI1_BUS_MIN, // StartBusNumber + CP2_PCI1_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + }, + { + CP2_PCI2_ECAM_BASE, // BaseAddress + 6, // PciSegmentGroupNumber + CP2_PCI2_BUS_MIN, // StartBusNumber + CP2_PCI2_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + } + } +}; + +VOID CONST * CONST ReferenceAcpiTable = &Mcfg; -- 2.29.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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