Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
> Benjamin Doron
> Sent: Thursday, July 22, 2021 7:27 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.c...@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desim...@intel.com>; Liming Gao
> <gaolim...@byosoft.com.cn>; Dong, Eric <eric.d...@intel.com>
> Subject: [edk2-devel] [PATCH v2] MinPlatformPkg/PciHostBridgeLibSimple:
> Fix Mem.Limit assignment
>
> In the case where the root bridge's Mem.Limit is the base address of PCIe
> MMIO, subtract one to make a valid end address.
>
> This fixes an issue where CpuDxe returns "Length(0x50000001) is not
> aligned!" when PciHostBridgeDxe attempts to make this range uncacheable.
>
> Cc: Chasel Chiu <chasel.c...@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
> Cc: Liming Gao <gaolim...@byosoft.com.cn>
> Cc: Eric Dong <eric.d...@intel.com>
> Signed-off-by: Benjamin Doron <benjamin.doro...@gmail.com>
> ---
>
> Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostB
> ridgeLibSimple.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos
> tBridgeLibSimple.c
> b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos
> tBridgeLibSimple.c
> index e231f747019e..0e3fee28b5d1 100644
> ---
> a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos
> tBridgeLibSimple.c
> +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/P
> +++ ciHostBridgeLibSimple.c
> @@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges (
> if (PcdGet32(PcdPciReservedMemLimit) != 0) {
> mRootBridgeTemplate.Mem.Limit = PcdGet32 (PcdPciReservedMemLimit);
> } else {- mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64
> (PcdPciExpressBaseAddress);+ mRootBridgeTemplate.Mem.Limit =
> (UINT32) PcdGet64 (PcdPciExpressBaseAddress) - 1; }
> mRootBridgeTemplate.MemAbove4G.Base = PcdGet64
> (PcdPciReservedMemAbove4GBBase);--
> 2.31.1
>
>
>
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