RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Tdx support 4-level paging or 5-level paging based on the GPAW. If 5-level page table is supported (GPAW is 52), a top level page directory pointers (1 * 256TB entry) is generated in the memory region defined by PcdOvmfSecPageTablesBase. Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org> Cc: Jordan Justen <jordan.l.jus...@intel.com> Cc: Brijesh Singh <brijesh.si...@amd.com> Cc: Erdem Aktas <erdemak...@google.com> Cc: James Bottomley <j...@linux.ibm.com> Cc: Jiewen Yao <jiewen....@intel.com> Cc: Tom Lendacky <thomas.lenda...@amd.com> Signed-off-by: Min Xu <min.m...@intel.com> --- OvmfPkg/ResetVector/ResetVector.nasmb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/ResetVector.nasmb index 42b4a3791d29..0ac6d7a6fd33 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -118,6 +118,9 @@ %define TDX_WORK_AREA_PGTBL_READY (TDX_WORK_AREA + 5) %define TDX_WORK_AREA_INITVP (TDX_WORK_AREA + 8) %define TDX_WORK_AREA_INFO (TDX_WORK_AREA + 8 + 4) + + %define TDX_PT_ADDR(Offset) (TDX_EXTRA_PAGE_TABLE_BASE + (Offset)) + %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset)) %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) -- 2.29.2.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78194): https://edk2.groups.io/g/devel/message/78194 Mute This Topic: https://groups.io/mt/84476062/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
