REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440
MM Configuration PPI was defined in PI Specification since v1.5. This
change added definition of such PPI and related GUIDs into MdePkg.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Cc: Michael Kubacki <michael.kuba...@microsoft.com>
Signed-off-by: Kun Qin <kuqi...@gmail.com>
---
Notes:
v2:
- Include PiMultiPhase.h instead of PiMmCis.h [Liming]
MdePkg/Include/Ppi/MmConfiguration.h | 62 ++++++++++++++++++++
MdePkg/MdePkg.dec | 3 +
2 files changed, 65 insertions(+)
diff --git a/MdePkg/Include/Ppi/MmConfiguration.h
b/MdePkg/Include/Ppi/MmConfiguration.h
new file mode 100644
index 000000000000..862a80e372f8
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmConfiguration.h
@@ -0,0 +1,62 @@
+/** @file
+ EFI MM Configuration PPI as defined in PI 1.5 specification.
+
+ This PPI is used to:
+ 1) report the portions of MMRAM regions which cannot be used for the MMRAM
heap.
+ 2) register the MM Foundation entry point with the processor code. The entry
+ point will be invoked by the MM processor entry code.
+
+ Copyright (c) Microsoft Corporation.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MM_CONFIGURATION_PPI_H_
+#define MM_CONFIGURATION_PPI_H_
+
+#include <Pi/PiMultiPhase.h>
+
+#define EFI_PEI_MM_CONFIGURATION_PPI_GUID \
+ { \
+ 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3,
0xa4 } \
+ }
+
+typedef struct _EFI_PEI_MM_CONFIGURATION_PPI EFI_PEI_MM_CONFIGURATION_PPI;
+
+/**
+ This function registers the MM Foundation entry point with the processor
code. This entry point will be
+ invoked by the MM Processor entry code as defined in PI specification.
+
+ @param[in] This The EFI_PEI_MM_CONFIGURATION_PPI instance.
+ @param[in] MmEntryPoint MM Foundation entry point.
+
+ @retval EFI_SUCCESS The entry-point was successfully registered.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY) (
+ IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This,
+ IN EFI_MM_ENTRY_POINT MmEntryPoint
+ );
+
+///
+/// This PPI is a PPI published by a CPU PEIM to indicate which areas within
MMRAM are reserved for use by
+/// the CPU for any purpose, such as stack, save state or MM entry point. If a
platform chooses to let a CPU
+/// PEIM do MMRAM relocation, this PPI must be produced by this CPU PEIM.
+///
+/// The MmramReservedRegions points to an array of one or more
EFI_MM_RESERVED_MMRAM_REGION structures, with
+/// the last structure having the MmramReservedSize set to 0. An empty array
would contain only the last
+/// structure.
+///
+/// The RegisterMmEntry() function allows the MM IPL PEIM to register the MM
Foundation entry point with the
+/// MM entry vector code.
+///
+struct _EFI_PEI_MM_CONFIGURATION_PPI {
+ EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions;
+ EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry;
+};
+
+extern EFI_GUID gEfiPeiMmConfigurationPpi;
+
+#endif
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index b49f88d8e18f..c5319fdd71ca 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -983,6 +983,9 @@ [Ppis]
## Include/Ppi/MmControl.h
gEfiPeiMmControlPpiGuid = { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d,
0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }}
+ ## Include/Ppi/MmConfiguration.h
+ gEfiPeiMmConfigurationPpi = { 0xc109319, 0xc149, 0x450e, { 0xa3,
0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } }
+
#
# PPIs defined in PI 1.7.
#
--
2.31.1.windows.1
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