Reviewed-by: Ray Ni <ray...@intel.com> > -----Original Message----- > From: Li, Daoxiang <daoxiang...@intel.com> > Sent: Wednesday, June 2, 2021 11:01 AM > To: devel@edk2.groups.io > Cc: Li, Daoxiang <daoxiang...@intel.com>; Dong, Eric <eric.d...@intel.com>; > Ni, Ray <ray...@intel.com>; Laszlo Ersek <ler...@redhat.com>; Kumar, > Rahul1 <rahul1.ku...@intel.com> > Subject: [PATCH v4 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Correct the > CPU location check > > From: Daoxiang Li <daoxiang...@intel.com> > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424 > > Processor location information check needs to updated > When Core 0 is disabled. > > In C1e.c, change MSR_FEATURE_CONFIG to MSR_NEHALEM_POWER_CTL in > comments > to match the correct MSR name. > > Signed-off-by: Daoxiang Li <daoxiang...@intel.com> > Cc: Eric Dong <eric.d...@intel.com> > Cc: Ray Ni <ray...@intel.com> > Cc: Laszlo Ersek <ler...@redhat.com> > Cc: Rahul Kumar <rahul1.ku...@intel.com> > --- > UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 4 ++-- > UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 4 ++-- > UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 6 +++--- > 3 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c > index e6e5db75917c..6f9685733202 100644 > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c > +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c > @@ -63,9 +63,9 @@ C1eInitialize ( > { > > // > > // The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is > Package, only program > > - // MSR_FEATURE_CONFIG for thread 0 core 0 in each package. > > + // MSR_NEHALEM_POWER_CTL once for each package. > > // > > - if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo- > >ProcessorInfo.Location.Core != 0)) { > > + if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) { > > return RETURN_SUCCESS; > > } > > > > diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c > index bb5d983d1f4b..a3a2861cee5b 100644 > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c > +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c > @@ -152,10 +152,10 @@ McaInitialize ( > > > // > > // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package > for below processor type, only program > > - // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in > each package. > > + // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS once for each package. > > // > > if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo- > >DisplayModel)) { > > - if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo- > >ProcessorInfo.Location.Core != 0)) { > > + if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) { > > return RETURN_SUCCESS; > > } > > } > > diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > index 8450c7ea3eaf..3c4c1bc706ba 100644 > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > @@ -130,10 +130,10 @@ PpinInitialize ( > // Support function already check the processor which support PPIN > feature, so this function not need > > // to check the processor again. > > // > > - // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only > program MSR_IVY_BRIDGE_PPIN_CTL for > > - // thread 0 core 0 in each package. > > + // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only > program MSR_IVY_BRIDGE_PPIN_CTL > > + // once for each package. > > // > > - if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo- > >ProcessorInfo.Location.Core != 0)) { > > + if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) { > > return RETURN_SUCCESS; > > } > > > > -- > 2.28.0.windows.1
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