REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3309
Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
(07h) data structure.
Signed-off-by: Jason Lou <yun....@intel.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Cc: Ray Ni <ray...@intel.com>
---
MdePkg/Include/Register/Intel/Cpuid.h | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/Register/Intel/Cpuid.h
b/MdePkg/Include/Register/Intel/Cpuid.h
index 19af99b6af..e7c0fd17e7 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -1550,9 +1550,17 @@ typedef union {
///
UINT32 AVX512_4FMAPS:1;
///
- /// [Bit 25:4] Reserved.
+ /// [Bit 14:4] Reserved.
///
- UINT32 Reserved2:22;
+ UINT32 Reserved2:11;
+ ///
+ /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.
+ ///
+ UINT32 Hybrid:1;
+ ///
+ /// [Bit 25:16] Reserved.
+ ///
+ UINT32 Reserved3:10;
///
/// [Bit 26] Enumerates support for indirect branch restricted speculation
/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
@@ -1581,7 +1589,7 @@ typedef union {
///
/// [Bit 30] Reserved.
///
- UINT32 Reserved3:1;
+ UINT32 Reserved4:1;
///
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable
(SSBD).
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They
allow
--
2.28.0.windows.1
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