On Wed, 2021-04-07 at 17:02 +0200, Laszlo Ersek wrote:
> On 04/07/21 02:44, James Bottomley wrote:
> > On Wed, 2021-04-07 at 00:21 +0000, Xu, Min M wrote:
> > > Hi, Laszlo
> > >
> > > For Intel TDX supported guest, all processors start in 32-bit
> > > protected mode, while for Non-Td guest, it starts in 16-bit real
> > > mode. To make the ResetVector work on both Td-guest and Non-Td
> > > guest, ResetVector are updated as below:
> > > ---------------------------------------------------------------
> > > ---
> > > ALIGN 16
> > > resetVector:
> > > ;
> > > ; Reset Vector
> > > ;
> > > ; This is where the processor will begin execution
> > > ;
> > > nop
> > > nop
> > > smsw ax
> > > test al, 1
> > > jnz EarlyBspPmEntry
> > > jmp EarlyBspInitReal16
> >
> > Well, then use the rel8 jump like the compiler would in this
> > situation:
> >
> > smsw ax
> > test al, 1
> > jz 1f
> > jmp EarlyBspPmEntry
> > 1:
> > jmp EarlyBspInitReal16
> >
> > So now both entries can be 32k away.
>
> The problem is that we need NASM to generate such *shared* entry code
> that behaves correctly when executed in either 16-bit or 32-bit mode.
>
> The rel8 near jumps ("short jumps") are like that -- for example, the
> "74 cb" opcode decodes to the same "JZ rel8" in both modes.
>
> But the rel16 ("non-short") near jumps turn into rel32 near jumps
> when decoded in 32-bit mode. For example, "E9 cw" decodes to "JMP
> rel16" in 16-bit mode, but it gets parsed as "E9 cd" (= "JMP rel32")
> in 32-bit mode.
>
> So the idea is to add more BITS directives, for covering the non-
> short near jumps themselves:
Absolutely ... sorry, I should have said this was just the first thing
I thought of. The key point is don't do a rel8 jump over the guid
table, use the rel8 jump within the reset vector to sort out the final
destination and use the wider jumps to go over the guid table. As you
say, we have to be very careful about the wider jumps given the
differences between the entry modes.
James
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