BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
Define the SEV-SNP MSR bits. Cc: James Bottomley <[email protected]> Cc: Min Xu <[email protected]> Cc: Jiewen Yao <[email protected]> Cc: Tom Lendacky <[email protected]> Cc: Jordan Justen <[email protected]> Cc: Ard Biesheuvel <[email protected]> Cc: Laszlo Ersek <[email protected]> Signed-off-by: Brijesh Singh <[email protected]> --- MdePkg/Include/Register/Amd/Fam17Msr.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h index e4db09c518..4d33bef220 100644 --- a/MdePkg/Include/Register/Amd/Fam17Msr.h +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -87,7 +87,12 @@ typedef union { /// UINT32 SevEsBit:1; - UINT32 Reserved:30; + /// + /// [Bit 2] Secure Nested Paging (SevSnp) is enabled + /// + UINT32 SevSnpBit:1; + + UINT32 Reserved:29; } Bits; /// /// All bit fields as a 32-bit value -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73219): https://edk2.groups.io/g/devel/message/73219 Mute This Topic: https://groups.io/mt/81584579/21656 Group Owner: [email protected] Unsubscribe: https://edk2.groups.io/g/devel/unsub [[email protected]] -=-=-=-=-=-=-=-=-=-=-=-
