This patch updates the OcteonTx device trees to the version
found in Linux v5.11. All previous modifications, compared
to vanilla files, are kept, i.e. disabled SPI flashes & RTC
and fixed-clock tree. Also enable the 10G ports and keep
AHCI node intact in order to avoid compatibility breakage.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
| 2 +-
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
| 2 +-
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
| 2 +-
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
| 43 --
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi
| 93 +++
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi
| 35 ++
Silicon/Marvell/OcteonTx/DeviceTree/T91/{armada-ap806.dtsi =>
armada-ap80x.dtsi} | 241 +++++++-
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
| 3 +-
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
| 552 -----------------
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi
| 12 +
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi
| 632 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
| 185 ------
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts
| 403 +++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
| 143 +----
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
| 29 -
Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9131-db.dtsi => cn9131-db.dts}
| 93 ++-
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
| 70 ---
Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9132-db.dtsi => cn9132-db.dts}
| 126 +++-
18 files changed, 1586 insertions(+), 1080 deletions(-)
delete mode 100644
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
create mode 100644
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi
rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{armada-ap806.dtsi =>
armada-ap80x.dtsi} (51%)
delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi
delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts
delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9131-db.dtsi =>
cn9131-db.dts} (66%)
delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9132-db.dtsi =>
cn9132-db.dts} (54%)
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
index 091a5b4..dfc6c32 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
@@ -16,7 +16,7 @@
VERSION_STRING = 1.0
[Sources]
- cn9130-db-A.dts
+ cn9130-db.dts
[Packages]
MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
index 8108197..f5c26a8 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
@@ -16,7 +16,7 @@
VERSION_STRING = 1.0
[Sources]
- cn9131-db-A.dts
+ cn9131-db.dts
[Packages]
MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
index c9e3b04..2796541 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
@@ -16,7 +16,7 @@
VERSION_STRING = 1.0
[Sources]
- cn9132-db-A.dts
+ cn9132-db.dts
[Packages]
MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
deleted file mode 100644
index bae0ed9..0000000
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include "armada-ap806.dtsi"
-
-/ {
- model = "Marvell Armada AP806 Quad";
- compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x000>;
- enable-method = "psci";
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x001>;
- enable-method = "psci";
- };
- cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x100>;
- enable-method = "psci";
- };
- cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x101>;
- enable-method = "psci";
- };
- };
-};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi
new file mode 100644
index 0000000..6222569
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for Marvell Armada AP807 Quad
+ *
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ */
+
+#include "armada-ap807.dtsi"
+
+/ {
+ model = "Marvell Armada AP807 Quad";
+ compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x000>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 0>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_0>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x001>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 0>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_0>;
+ };
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 1>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ };
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x101>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 1>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi
new file mode 100644
index 0000000..0b36eb8
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for Marvell Armada AP807
+ *
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ */
+
+#define AP_NAME ap807
+#include "armada-ap80x.dtsi"
+
+/ {
+ model = "Marvell Armada AP807";
+ compatible = "marvell,armada-ap807";
+};
+
+&ap_syscon0 {
+ ap_clk: clock {
+ compatible = "marvell,ap807-clock";
+ #clock-cells = <1>;
+ };
+};
+
+&ap_syscon1 {
+ cpu_clk: clock-cpu {
+ compatible = "marvell,ap807-cpu-clock";
+ clocks = <&ap_clk 0>, <&ap_clk 1>;
+ #clock-cells = <1>;
+ };
+};
+
+&ap_sdhci0 {
+ compatible = "marvell,armada-ap807-sdhci",
+ "marvell,armada-ap806-sdhci"; /* Backward compatibility */
+};
+
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi
similarity index 51%
rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi
index 66124bf..805d782 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
*
- * Device Tree file for Marvell Armada AP806.
+ * Device Tree file for Marvell Armada AP80x.
*/
#define IRQ_TYPE_LEVEL_HIGH (1 << 2)
@@ -14,11 +14,12 @@
#define GIC_CPU_MASK_RAW(x) ((x) << 8)
#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
/dts-v1/;
/ {
- model = "Marvell Armada AP806";
- compatible = "marvell,armada-ap806";
#address-cells = <2>;
#size-cells = <2>;
@@ -34,7 +35,24 @@
method = "smc";
};
- ap806 {
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * This area matches the mapping done with a
+ * mainline U-Boot, and should be updated by the
+ * bootloader.
+ */
+
+ psci-area@4000000 {
+ reg = <0x0 0x4000000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ AP_NAME {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
@@ -47,6 +65,24 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf0000000 0x1000000>;
+ smmu: iommu@5000000 {
+ compatible = "marvell,ap806-smmu-500",
"arm,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -131,6 +167,15 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
+ sei: interrupt-controller@3f0200 {
+ compatible = "marvell,ap806-sei";
+ reg = <0x3f0200 0x40>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ msi-controller;
+ };
+
xor@400000 {
compatible = "marvell,armada-7k-xor",
"marvell,xor-v2";
reg = <0x400000 0x1000>,
@@ -183,7 +228,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&ap_clk 3>;
status = "disabled";
};
@@ -226,15 +270,10 @@
status = "disabled";
};
- ap_syscon: system-controller@6f4000 {
+ ap_syscon0: system-controller@6f4000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x2000>;
- ap_clk: clock {
- compatible = "marvell,ap806-clock";
- #clock-cells = <1>;
- };
-
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
@@ -251,13 +290,183 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&ap_pinctrl 0 0 20>;
+ marvell,pwm-offset = <0x10c0>;
+ #pwm-cells = <2>;
+ clocks = <&ap_clk 3>;
+ };
+ };
+
+ ap_syscon1: system-controller@6f8000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f8000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ap_thermal: thermal-sensor@80 {
+ compatible =
"marvell,armada-ap806-thermal";
+ reg = <0x80 0x10>;
+ interrupt-parent = <&sei>;
+ interrupts = <18>;
+ #thermal-sensor-cells = <1>;
};
};
+ };
+ };
- ap_thermal: thermal@6f808c {
- compatible = "marvell,armada-ap806-thermal";
- reg = <0x6f808c 0x4>,
- <0x6f8084 0x8>;
+ /*
+ * The thermal IP features one internal sensor plus, if applicable, one
+ * remote channel wired to one sensor per CPU.
+ *
+ * Only one thermal zone per AP/CP may trigger interrupts at a time,
the
+ * first one that will have a critical trip point will be chosen.
+ */
+ thermal-zones {
+ ap_thermal_ic: ap-thermal-ic {
+ polling-delay-passive = <0>; /* Interrupt driven */
+ polling-delay = <0>; /* Interrupt driven */
+
+ thermal-sensors = <&ap_thermal 0>;
+
+ trips {
+ ap_crit: ap-crit {
+ temperature = <100000>; /* mC degrees
*/
+ hysteresis = <2000>; /* mC degrees */
+ type = "critical";
+ };
+ };
+
+ cooling-maps { };
+ };
+
+ ap_thermal_cpu0: ap-thermal-cpu0 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&ap_thermal 1>;
+
+ trips {
+ cpu0_hot: cpu0-hot {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu0_emerg: cpu0-emerg {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0_hot: map0-hot {
+ trip = <&cpu0_hot>;
+ cooling-device = <&cpu0 1 2>,
+ <&cpu1 1 2>;
+ };
+ map0_emerg: map0-ermerg {
+ trip = <&cpu0_emerg>;
+ cooling-device = <&cpu0 3 3>,
+ <&cpu1 3 3>;
+ };
+ };
+ };
+
+ ap_thermal_cpu1: ap-thermal-cpu1 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&ap_thermal 2>;
+
+ trips {
+ cpu1_hot: cpu1-hot {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu1_emerg: cpu1-emerg {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map1_hot: map1-hot {
+ trip = <&cpu1_hot>;
+ cooling-device = <&cpu0 1 2>,
+ <&cpu1 1 2>;
+ };
+ map1_emerg: map1-emerg {
+ trip = <&cpu1_emerg>;
+ cooling-device = <&cpu0 3 3>,
+ <&cpu1 3 3>;
+ };
+ };
+ };
+
+ ap_thermal_cpu2: ap-thermal-cpu2 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&ap_thermal 3>;
+
+ trips {
+ cpu2_hot: cpu2-hot {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu2_emerg: cpu2-emerg {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map2_hot: map2-hot {
+ trip = <&cpu2_hot>;
+ cooling-device = <&cpu2 1 2>,
+ <&cpu3 1 2>;
+ };
+ map2_emerg: map2-emerg {
+ trip = <&cpu2_emerg>;
+ cooling-device = <&cpu2 3 3>,
+ <&cpu3 3 3>;
+ };
+ };
+ };
+
+ ap_thermal_cpu3: ap-thermal-cpu3 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&ap_thermal 4>;
+
+ trips {
+ cpu3_hot: cpu3-hot {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu3_emerg: cpu3-emerg {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map3_hot: map3-bhot {
+ trip = <&cpu3_hot>;
+ cooling-device = <&cpu2 1 2>,
+ <&cpu3 1 2>;
+ };
+ map3_emerg: map3-emerg {
+ trip = <&cpu3_emerg>;
+ cooling-device = <&cpu2 3 3>,
+ <&cpu3 3 3>;
+ };
};
};
};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
index 8b610fd..f002499 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
@@ -6,5 +6,6 @@
/* Common definitions used by Armada 7K/8K DTs */
#define PASTER(x, y) x ## y
#define EVALUATOR(x, y) PASTER(x, y)
-#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
+#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
deleted file mode 100644
index b6e5ded..0000000
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
+++ /dev/null
@@ -1,552 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for Marvell Armada CP110.
- */
-
-#include "armada-common.dtsi"
-
-#define ICU_GRP_NSR 0x0
-#define ICU_GRP_SR 0x1
-#define ICU_GRP_SEI 0x4
-#define ICU_GRP_REI 0x5
-
-#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) +
0xf00000)
-
-/ {
- /*
- * The contents of the node are defined below, in order to
- * save one indentation level
- */
- CP110_NAME: CP110_NAME { };
-};
-
-&CP110_NAME {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&CP110_LABEL(icu)>;
- ranges;
-
- config-space@CP110_BASE {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
-
- CP110_LABEL(ethernet): ethernet@0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&CP110_LABEL(ppv2_clk)>,
<&CP110_LABEL(ppv2_clk)>,
- <&CP110_LABEL(ppv2_clk)>,
<&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(core_clk)>;
- clock-names = "pp_clk", "gop_clk",
- "mg_clk", "mg_core_clk", "axi_clk";
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- status = "disabled";
- dma-coherent;
-
- CP110_LABEL(eth0): eth0 {
- interrupts = <ICU_GRP_NSR 39
IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1",
"tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- CP110_LABEL(eth1): eth1 {
- interrupts = <ICU_GRP_NSR 40
IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1",
"tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- CP110_LABEL(eth2): eth2 {
- interrupts = <ICU_GRP_NSR 41
IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1",
"tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- CP110_LABEL(comphy): phy@120000 {
- compatible = "marvell,comphy-cp110";
- reg = <0x120000 0x6000>;
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- CP110_LABEL(comphy0): phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy1): phy@1 {
- reg = <1>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy2): phy@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy3): phy@3 {
- reg = <3>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy4): phy@4 {
- reg = <4>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy5): phy@5 {
- reg = <5>;
- #phy-cells = <1>;
- };
- };
-
- CP110_LABEL(mdio): mdio@12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- clocks = <&CP110_LABEL(ppv2_clk)>,
<&CP110_LABEL(ppv2_clk)>,
- <&CP110_LABEL(core_clk)>,
<&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(xmdio): mdio@12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x10>;
- clocks = <&CP110_LABEL(ppv2_clk)>,
<&CP110_LABEL(ppv2_clk)>,
- <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(icu): interrupt-controller@1e0000 {
- compatible = "marvell,cp110-icu";
- reg = <0x1e0000 0x440>;
- #interrupt-cells = <3>;
- interrupt-controller;
- msi-parent = <&gicp>;
- };
-
- CP110_LABEL(rtc): rtc@284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- CP110_LABEL(thermal): thermal@400078 {
- compatible = "marvell,armada-cp110-thermal";
- reg = <0x400078 0x4>,
- <0x400070 0x8>;
- };
-
- CP110_LABEL(syscon0): system-controller@440000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x440000 0x2000>;
-
- CP110_LABEL(clk): clock {
- compatible = "marvell,cp110-clock";
- status = "disabled";
- #clock-cells = <2>;
- };
-
- CP110_LABEL(gpio1): gpio@100 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x100>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
- interrupt-controller;
- interrupts = <ICU_GRP_NSR 86
IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- CP110_LABEL(gpio2): gpio@140 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x140>;
- ngpios = <31>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
- interrupt-controller;
- interrupts = <ICU_GRP_NSR 82
IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- };
-
- CP110_LABEL(usb3_0): usb3@500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(usb3_1): usb3@510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(sata0): sata@540000 {
- compatible = "marvell,armada-8k-ahci",
- "generic-ahci";
- reg = <0x540000 0x30000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(xor0): xor@6a0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- };
-
- CP110_LABEL(xor1): xor@6c0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- };
-
- CP110_LABEL(spi0): spi@700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(spi1): spi@700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(i2c0): i2c@701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(i2c1): i2c@701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(uart0): serial@702000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702000 0x100>;
- reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(uart1): serial@702100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702100 0x100>;
- reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(uart2): serial@702200 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702200 0x100>;
- reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(uart3): serial@702300 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702300 0x100>;
- reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(slow_io_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(nand_controller): nand@720000 {
- /*
- * Due to the limitation of the pins available
- * this controller is only usable on the CPM
- * for A7K and on the CPS for A8K.
- */
- compatible = "marvell,armada-8k-nand-controller",
- "marvell,armada370-nand-controller";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(nand_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- status = "disabled";
- };
-
- CP110_LABEL(trng): trng@760000 {
- compatible = "marvell,armada-8k-rng",
- "inside-secure,safexcel-eip76";
- reg = <0x760000 0x7d>;
- interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(x2core_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- status = "okay";
- };
-
- CP110_LABEL(sdhci0): sdhci@780000 {
- compatible = "marvell,armada-cp110-sdhci";
- reg = <0x780000 0x300>;
- interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(sdio_clk)>,
<&CP110_LABEL(core_clk)>;
- dma-coherent;
- status = "disabled";
- };
-
- CP110_LABEL(crypto): crypto@800000 {
- compatible = "inside-secure,safexcel-eip197";
- reg = <0x800000 0x200000>;
- interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mem", "ring0", "ring1",
- "ring2", "ring3", "eip";
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(x2core_clk)>,
- <&CP110_LABEL(x2core_clk)>;
- dma-coherent;
- };
- };
-
- CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* non-prefetchable memory */
- <0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0
CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22
IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* non-prefetchable memory */
- <0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0
CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24
IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* non-prefetchable memory */
- <0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0
CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23
IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
- status = "disabled";
- };
-
- /* 1 GHz fixed main PLL */
- CP110_LABEL(mainpll): CP110_LABEL(mainpll) {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000000>;
- };
-
- CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- CP110_LABEL(core_clk): CP110_LABEL(core_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <2>;
- clock-div = <5>;
- };
-
- CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <2>;
- clock-div = <5>;
- };
-
- CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) {
- compatible = "fixed-factor-clock";
- clocks = <&CP110_LABEL(mainpll)>;
- #clock-cells = <0>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi
new file mode 100644
index 0000000..f57860f
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP115.
+ */
+
+#define CP11X_TYPE cp115
+
+#include "armada-cp11x.dtsi"
+
+#undef CP11X_TYPE
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi
new file mode 100644
index 0000000..c309aaa
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP11x.
+ */
+
+#include "armada-common.dtsi"
+
+#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) +
CP11X_PCIEx_MEM_SIZE(iface))
+
+/ {
+ /*
+ * The contents of the node are defined below, in order to
+ * save one indentation level
+ */
+ CP11X_NAME: CP11X_NAME { };
+
+ /*
+ * CPs only have one sensor in the thermal IC.
+ *
+ * The cooling maps are empty as there are no cooling devices.
+ */
+ thermal-zones {
+ CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
+ polling-delay-passive = <0>; /* Interrupt driven */
+ polling-delay = <0>; /* Interrupt driven */
+
+ thermal-sensors = <&CP11X_LABEL(thermal) 0>;
+
+ trips {
+ CP11X_LABEL(crit): crit {
+ temperature = <100000>; /* mC degrees
*/
+ hysteresis = <2000>; /* mC degrees */
+ type = "critical";
+ };
+ };
+
+ cooling-maps { };
+ };
+ };
+};
+
+&CP11X_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
+ ranges;
+
+ config-space@CP11X_BASE {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
+
+ CP11X_LABEL(ethernet): ethernet@0 {
+ compatible = "marvell,armada-7k-pp22";
+ reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000
0x800>;
+ clocks = <&CP11X_LABEL(ppv2_clk)>,
<&CP11X_LABEL(ppv2_clk)>,
+ <&CP11X_LABEL(ppv2_clk)>,
<&CP11X_LABEL(core_clk)>,
+ <&CP11X_LABEL(core_clk)>;
+ clock-names = "pp_clk", "gop_clk",
+ "mg_clk", "mg_core_clk", "axi_clk";
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ status = "disabled";
+ dma-coherent;
+
+ CP11X_LABEL(eth0): eth0 {
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
+ <43 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <51 IRQ_TYPE_LEVEL_HIGH>,
+ <55 IRQ_TYPE_LEVEL_HIGH>,
+ <59 IRQ_TYPE_LEVEL_HIGH>,
+ <63 IRQ_TYPE_LEVEL_HIGH>,
+ <67 IRQ_TYPE_LEVEL_HIGH>,
+ <71 IRQ_TYPE_LEVEL_HIGH>,
+ <129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2",
+ "hif3", "hif4", "hif5", "hif6", "hif7",
+ "hif8", "link";
+ port-id = <0>;
+ gop-port-id = <0>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(eth1): eth1 {
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
+ <44 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>,
+ <52 IRQ_TYPE_LEVEL_HIGH>,
+ <56 IRQ_TYPE_LEVEL_HIGH>,
+ <60 IRQ_TYPE_LEVEL_HIGH>,
+ <64 IRQ_TYPE_LEVEL_HIGH>,
+ <68 IRQ_TYPE_LEVEL_HIGH>,
+ <72 IRQ_TYPE_LEVEL_HIGH>,
+ <128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2",
+ "hif3", "hif4", "hif5", "hif6", "hif7",
+ "hif8", "link";
+ port-id = <1>;
+ gop-port-id = <2>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(eth2): eth2 {
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
+ <45 IRQ_TYPE_LEVEL_HIGH>,
+ <49 IRQ_TYPE_LEVEL_HIGH>,
+ <53 IRQ_TYPE_LEVEL_HIGH>,
+ <57 IRQ_TYPE_LEVEL_HIGH>,
+ <61 IRQ_TYPE_LEVEL_HIGH>,
+ <65 IRQ_TYPE_LEVEL_HIGH>,
+ <69 IRQ_TYPE_LEVEL_HIGH>,
+ <73 IRQ_TYPE_LEVEL_HIGH>,
+ <127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2",
+ "hif3", "hif4", "hif5", "hif6", "hif7",
+ "hif8", "link";
+ port-id = <2>;
+ gop-port-id = <3>;
+ status = "disabled";
+ };
+ };
+
+ CP11X_LABEL(comphy): phy@120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ clocks = <&CP11X_LABEL(ppv2_clk)>,
<&CP11X_LABEL(core_clk)>,
+ <&CP11X_LABEL(core_clk)>;
+ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CP11X_LABEL(comphy0): phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy1): phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy2): phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy3): phy@3 {
+ reg = <3>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy4): phy@4 {
+ reg = <4>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy5): phy@5 {
+ reg = <5>;
+ #phy-cells = <1>;
+ };
+ };
+
+ CP11X_LABEL(mdio): mdio@12a200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ clocks = <&CP11X_LABEL(ppv2_clk)>,
<&CP11X_LABEL(ppv2_clk)>,
+ <&CP11X_LABEL(core_clk)>,
<&CP11X_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(xmdio): mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x10>;
+ clocks = <&CP11X_LABEL(ppv2_clk)>,
<&CP11X_LABEL(ppv2_clk)>,
+ <&CP11X_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(icu): interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x440>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ CP11X_LABEL(icu_nsr): interrupt-controller@10 {
+ compatible = "marvell,cp110-icu-nsr";
+ reg = <0x10 0x20>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
+ CP11X_LABEL(icu_sei): interrupt-controller@50 {
+ compatible = "marvell,cp110-icu-sei";
+ reg = <0x50 0x10>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&sei>;
+ };
+ };
+
+ CP11X_LABEL(rtc): rtc@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(syscon0): system-controller@440000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x440000 0x2000>;
+
+ CP11X_LABEL(clk): clock {
+ compatible = "marvell,cp110-clock";
+ status = "disabled";
+ #clock-cells = <2>;
+ };
+
+ CP11X_LABEL(gpio1): gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
+ marvell,pwm-offset = <0x1f0>;
+ #pwm-cells = <2>;
+ interrupt-controller;
+ interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
+ <85 IRQ_TYPE_LEVEL_HIGH>,
+ <84 IRQ_TYPE_LEVEL_HIGH>,
+ <83 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(gpio2): gpio@140 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x140>;
+ ngpios = <31>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
+ marvell,pwm-offset = <0x1f0>;
+ #pwm-cells = <2>;
+ interrupt-controller;
+ interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
+ <81 IRQ_TYPE_LEVEL_HIGH>,
+ <80 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+ };
+
+ CP11X_LABEL(syscon1): system-controller@400000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x400000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ CP11X_LABEL(thermal): thermal-sensor@70 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x70 0x10>;
+ interrupts-extended =
+ <&CP11X_LABEL(icu_sei) 116
IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ CP11X_LABEL(usb3_0): usb@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(core_clk)>,
+ <&CP11X_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(usb3_1): usb@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(core_clk)>,
+ <&CP11X_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(sata0): sata@540000 {
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
+ reg = <0x540000 0x30000>;
+ dma-coherent;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP11X_LABEL(core_clk)>,
+ <&CP11X_LABEL(core_clk)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ };
+
+ sata-port@1 {
+ reg = <1>;
+ };
+ };
+
+ CP11X_LABEL(xor0): xor@6a0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(core_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ };
+
+ CP11X_LABEL(xor1): xor@6c0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(core_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ };
+
+ CP11X_LABEL(spi0): spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(spi1): spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(i2c0): i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(i2c1): i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(uart0): serial@702000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702000 0x100>;
+ reg-shift = <2>;
+ interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(uart1): serial@702100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702100 0x100>;
+ reg-shift = <2>;
+ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(uart2): serial@702200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702200 0x100>;
+ reg-shift = <2>;
+ interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(uart3): serial@702300 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702300 0x100>;
+ reg-shift = <2>;
+ interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(nand_controller): nand@720000 {
+ /*
+ * Due to the limitation of the pins available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(nand_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(trng): trng@760000 {
+ compatible = "marvell,armada-8k-rng",
+ "inside-secure,safexcel-eip76";
+ reg = <0x760000 0x7d>;
+ interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(x2core_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ status = "okay";
+ };
+
+ CP11X_LABEL(sdhci0): sdhci@780000 {
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(sdio_clk)>,
<&CP11X_LABEL(core_clk)>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(crypto): crypto@800000 {
+ compatible = "inside-secure,safexcel-eip197b";
+ reg = <0x800000 0x200000>;
+ interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
+ <88 IRQ_TYPE_LEVEL_HIGH>,
+ <89 IRQ_TYPE_LEVEL_HIGH>,
+ <90 IRQ_TYPE_LEVEL_HIGH>,
+ <91 IRQ_TYPE_LEVEL_HIGH>,
+ <92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1",
+ "ring2", "ring3", "eip";
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(x2core_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
+ dma-coherent;
+ };
+ };
+
+ CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
+ <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0
CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
+ <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0
CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
+ <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0
CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ /* 1 GHz fixed main PLL */
+ CP11X_LABEL(mainpll): CP11X_LABEL(mainpll) {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ CP11X_LABEL(x2core_clk): CP11X_LABEL(x2core_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP11X_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ CP11X_LABEL(core_clk): CP11X_LABEL(core_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP11X_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ CP11X_LABEL(sdio_clk): CP11X_LABEL(sdio_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP11X_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <2>;
+ clock-div = <5>;
+ };
+
+ CP11X_LABEL(nand_clk): CP11X_LABEL(nand_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP11X_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <2>;
+ clock-div = <5>;
+ };
+
+ CP11X_LABEL(ppv2_clk): CP11X_LABEL(ppv2_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP11X_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ CP11X_LABEL(slow_io_clk): CP11X_LABEL(slow_io_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP11X_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
deleted file mode 100644
index 9e4aa51..0000000
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright (C) 2018 Marvell International Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0
- * https://spdx.org/licenses
- */
-
-#include "cn9130-db.dtsi"
-
-/ {
- model = "Model: Marvell CN9130 development board (CP NOR) setup(A)";
- compatible = "marvell,cn9130-db-A", "marvell,armada-ap807-quad",
- "marvell,armada-ap807";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- i2c0 = &cp0_i2c0;
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp0_eth1;
- ethernet2 = &cp0_eth2;
- };
-
- memory@00000000 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-/* on-board eMMC - U9 */
-&ap_sdhci0 {
- pinctrl-names = "default";
- bus-width = <8>;
- status = "okay";
- vqmmc-supply = <&ap0_reg_sd_vccq>;
-};
-
-/*
- * CP related configuration
- */
-&cp0_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c0_pins>;
- status = "okay";
- clock-frequency = <100000>;
-};
-
-&cp0_i2c1 {
- status = "okay";
-};
-
-/* CON 28 */
-&cp0_sdhci0 {
- status = "okay";
-};
-
-/* U54 */
-&cp0_nand_controller {
- pinctrl-names = "default";
- pinctrl-0 = <&nand_pins>;
-
- nand@0 {
- reg = <0>;
- label = "main-storage";
- nand-rb = <0>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
- nand-ecc-strength = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition@200000 {
- label = "Linux";
- reg = <0x200000 0xd00000>;
- };
- partition@1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
- };
- };
- };
-};
-
-/* U55 */
-&cp0_spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi0_pins>;
- reg = <0x700680 0x50>, /* control */
- <0x2000000 0x1000000>; /* CS0 */
- status = "disabled";
-
- spi-flash@0 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- /* On-board MUX does not allow higher frequencies */
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0x0 0x200000>;
- };
-
- partition@400000 {
- label = "Filesystem";
- reg = <0x200000 0xe00000>;
- };
- };
- };
-};
-
-/* SLM-1521-V2, CON6 */
-&cp0_pcie0 {
- status = "okay";
- num-lanes = <4>;
- num-viewport = <8>;
- /* Generic PHY, providing serdes lanes */
- phys = <&cp0_comphy0 0
- &cp0_comphy1 0
- &cp0_comphy2 0
- &cp0_comphy3 0>;
-};
-
-&cp0_sata0 {
- status = "okay";
- /* SLM-1521-V2, CON2 */
-};
-
-&cp0_mdio {
- status = "okay";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-/* SLM-1521-V2, CON9 */
-&cp0_eth0 {
- status = "okay";
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp0_comphy4 0>;
- managed = "in-band-status";
- sfp = <&cp0_sfp_eth0>;
-};
-
-/* CON56 */
-&cp0_eth1 {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
-};
-
-/* CON57 */
-&cp0_eth2 {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
-};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts
new file mode 100644
index 0000000..7f54f36
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board.
+ */
+
+#include "cn9130.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ap0_reg_sd_vccq: ap0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy0: cp0_usb3_phy@0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus0>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy1: cp0_usb3_phy@1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus1>;
+ };
+
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ cp0_sfp_eth0: sfp-eth@0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_sfpp0_i2c>;
+ los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the
I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ status = "disabled";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ vqmmc-supply = <&ap0_reg_sd_vccq>;
+ status = "okay";
+};
+
+&cp0_crypto {
+ status = "disabled";
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp0_sfp_eth0>;
+};
+
+/* CON56 */
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+/* CON57 */
+&cp0_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+
+ /* U36 */
+ expander0: pca953x@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ status = "okay";
+ };
+
+ /* U42 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U38 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
+};
+
+&cp0_i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 { /* verify address - depends on dpr */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp0_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp0_module_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+
+ };
+ };
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+/* U54 */
+&cp0_nand_controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins &nand_rb>;
+
+ nand@0 {
+ reg = <0>;
+ label = "main-storage";
+ nand-rb = <0>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xd00000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
+ };
+};
+
+/* SLM-1521-V2, CON6 */
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0
+ &cp0_comphy1 0
+ &cp0_comphy2 0
+ &cp0_comphy3 0>;
+};
+
+&cp0_sata0 {
+ status = "okay";
+
+ /* SLM-1521-V2, CON2 */
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy5 1>;
+ };
+};
+
+/* CON 28 */
+&cp0_sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+};
+
+/* U55 */
+&cp0_spi1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>;
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot-0";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem-0";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11";
+ marvell,function = "ge0";
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = "mpp44", "mpp45", "mpp46",
+ "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52",
+ "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ nand_pins: nand-pins {
+ marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
+ "mpp19", "mpp20", "mpp21", "mpp22",
+ "mpp23", "mpp24", "mpp25", "mpp26",
+ "mpp27";
+ marvell,function = "dev";
+ };
+ nand_rb: nand-rb {
+ marvell,pins = "mpp13";
+ marvell,function = "nf";
+ };
+ };
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
index 97ea923..6187a34 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
@@ -1,126 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2019 Marvell International Ltd.
*
- * SPDX-License-Identifier: GPL-2.0
- * https://spdx.org/licenses
+ * Device tree for the CN9130 SoC.
*/
-/*
- * Device Tree file for the CN 9130 SoC, made of an AP807 Quad and
- * three CP110.
- */
-
-#include "armada-ap806-quad.dtsi"
-
-/ {
- aliases {
- gpio1 = &cp0_gpio1;
- gpio2 = &cp0_gpio2;
- spi1 = &cp0_spi0;
- spi2 = &cp0_spi1;
- };
-};
-
-/* This defines used to calculate the base address of each CP */
-#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
-#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
-
-/* CP110-0 Settings */
-#define CP110_NAME cp0
-#define CP110_NUM 0
-#define CP110_BASE f2000000
-#define CP110_PCIE0_BASE f2600000
-#define CP110_PCIE1_BASE f2620000
-#define CP110_PCIE2_BASE f2640000
-#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
- (0xe0000000 + (iface - 1) *
0x1000000))
-#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
-
-#include "armada-cp110.dtsi"
-
-#undef CP110_NUM
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
+#include "armada-ap807-quad.dtsi"
/ {
- model = "Marvell CN 9130";
+ model = "Marvell Armada CN9130 SoC";
compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
- "marvell,armada-ap806";
+ "marvell,armada-ap807";
};
-&cp0_crypto {
- status = "okay";
-};
-
-&cp0_gpio1 {
- status = "okay";
-};
-
-&cp0_gpio2 {
- status = "okay";
-};
-
-&cp0_syscon0 {
- cp0_pinctrl: pinctrl {
- compatible = "marvell,armada-7k-pinctrl";
-
- cp0_devbus_pins: cp0-devbus-pins {
- marvell,pins = "mpp15", "mpp16", "mpp17",
- "mpp18", "mpp19", "mpp20",
- "mpp21", "mpp22", "mpp23",
- "mpp24", "mpp25", "mpp26",
- "mpp27";
- marvell,function = "dev";
- };
+/*
+ * Instantiate the internal CP115
+ */
- cp0_i2c0_pins: cp0-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp0_i2c1_pins: cp0-i2c-pins-1 {
- marvell,pins = "mpp35", "mpp36";
- marvell,function = "i2c1";
- };
- cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
- marvell,pins = "mpp0", "mpp1", "mpp2",
- "mpp3", "mpp4", "mpp5",
- "mpp6", "mpp7", "mpp8",
- "mpp9", "mpp10", "mpp11";
- marvell,function = "ge0";
- };
- cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
- marvell,pins = "mpp44", "mpp45", "mpp46",
- "mpp47", "mpp48", "mpp49",
- "mpp50", "mpp51", "mpp52",
- "mpp53", "mpp54", "mpp55";
- marvell,function = "ge1";
- };
- cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
- marvell,pins = "mpp43";
- marvell,function = "gpio";
- };
- cp0_sdhci_pins: cp0-sdhi-pins-0 {
- marvell,pins = "mpp56", "mpp57", "mpp58",
- "mpp59", "mpp60", "mpp61";
- marvell,function = "sdio";
- };
- cp0_spi0_pins: cp0-spi-pins-0 {
- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
- nand_pins: nand-pins {
- marvell,pins =
- "mpp15", "mpp16", "mpp17", "mpp18", "mpp19",
- "mpp20", "mpp21", "mpp22", "mpp23", "mpp24",
- "mpp25", "mpp26", "mpp27";
- marvell,function = "dev";
- };
- nand_rb: nand-rb {
- marvell,pins = "mpp13";
- marvell,function = "nf";
- };
- };
-};
+#define CP11X_NAME cp0
+#define CP11X_BASE f2000000
+#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+ 0xe0000000 + ((iface - 1)
* 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP11X_PCIE0_BASE f2600000
+#define CP11X_PCIE1_BASE f2620000
+#define CP11X_PCIE2_BASE f2640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
deleted file mode 100644
index f08a748..0000000
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2018 Marvell International Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0
- * https://spdx.org/licenses
- */
-
-#include "cn9130-db-A.dts"
-#include "cn9131-db.dtsi"
-
-/ {
- model = "Marvell CN9131 development board (CP NOR) setup(A)";
- compatible = "marvell,cn9131-db-A", "marvell,armada-ap807-quad",
- "marvell,armada-ap807";
-};
-
-&cp1_ethernet {
- status = "okay";
-};
-
-/* CON50 */
-&cp1_eth0 {
- status = "okay";
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy4 0>;
- managed = "in-band-status";
- sfp = <&cp1_sfp_eth1>;
-};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts
similarity index 66%
rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts
index 9c9dfb6..3d5a67e 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts
@@ -1,35 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2019 Marvell International Ltd.
*
- * SPDX-License-Identifier: GPL-2.0
- * https://spdx.org/licenses
+ * Device tree for the CN9131-DB board.
*/
-#undef CP110_NUM
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
-#undef CP110_PCIEx_CPU_MEM_BASE
-#undef CP110_PCIEx_MEM_BASE
-
-/* CP110-1 Settings */
-#define CP110_NAME cp1
-#define CP110_NUM 1
-#define CP110_BASE f4000000
-#define CP110_PCIE0_BASE f4600000
-#define CP110_PCIE1_BASE f4620000
-#define CP110_PCIE2_BASE f4640000
-#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
-#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
-
-#include "armada-cp110.dtsi"
+#include "cn9130-db.dts"
/ {
- model = "Marvell CN9131 development board";
- compatible = "marvell,cn9131-db", "marvell,armada-ap807-quad",
- "marvell,armada-ap807";
+ model = "Marvell Armada CN9131-DB";
+ compatible = "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
aliases {
gpio3 = &cp1_gpio1;
@@ -63,12 +44,53 @@
tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cp1_sfp_pins>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the
I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
status = "disabled";
};
};
+/*
+ * Instantiate the first slave CP115
+ */
+
+#define CP11X_NAME cp1
+#define CP11X_BASE f4000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f4600000
+#define CP11X_PCIE1_BASE f4620000
+#define CP11X_PCIE2_BASE f4640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
&cp1_crypto {
+ status = "disabled";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp1_sfp_eth1>;
};
&cp1_gpio1 {
@@ -80,9 +102,9 @@
};
&cp1_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_i2c0_pins>;
- status = "okay";
clock-frequency = <100000>;
};
@@ -101,15 +123,20 @@
&cp1_sata0 {
status = "okay";
+
+ /* CON32 */
+ sata-port@1 {
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy5 1>;
+ };
};
/* U24 */
&cp1_spi1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_spi0_pins>;
- reg = <0x700680 0x50>, /* control */
- <0x2000000 0x1000000>; /* CS0 */
- status = "okay";
+ reg = <0x700680 0x50>;
spi-flash@0 {
#address-cells = <0x1>;
@@ -125,12 +152,12 @@
#size-cells = <1>;
partition@0 {
- label = "U-Boot";
+ label = "U-Boot-1";
reg = <0x0 0x200000>;
};
partition@400000 {
- label = "Filesystem";
+ label = "Filesystem-1";
reg = <0x200000 0xe00000>;
};
};
@@ -140,7 +167,7 @@
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
- compatible = "marvell,armada-7k-pinctrl";
+ compatible = "marvell,cp115-standalone-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
deleted file mode 100644
index 724d7dc..0000000
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * copyright (c) 2019 marvell international ltd.
- *
- * spdx-license-identifier: gpl-2.0
- * https://spdx.org/licenses
- */
-
-#include "cn9131-db-A.dts"
-#include "cn9132-db.dtsi"
-
-/ {
- model = "Model: Marvell CN9132 development board (CP NOR) setup(A)";
- compatible = "marvell,cn9132-db-A", "marvell,armada-ap807-quad",
- "marvell,armada-ap807";
-
- aliases {
- gpio5 = &cp2_gpio1;
- gpio6 = &cp2_gpio2;
- ethernet5 = &cp2_eth0;
- };
-};
-
-&cp2_ethernet {
- status = "okay";
-};
-
-/* SLM-1521-V2, CON9 */
-&cp2_eth0 {
- status = "okay";
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy4 0>;
- managed = "in-band-status";
- sfp = <&cp2_sfp_eth0>;
-};
-
-/* SLM-1521-V2, CON6 */
-&cp2_pcie0 {
- status = "okay";
- num-lanes = <2>;
- num-viewport = <8>;
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy0 0
- &cp2_comphy1 0>;
-};
-
-/* SLM-1521-V2, CON8 */
-&cp2_pcie2 {
- status = "okay";
- num-lanes = <1>;
- num-viewport = <8>;
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy5 2>;
-};
-
-&cp2_sata0 {
- status = "okay";
-};
-
-/* CON 2 on SLM-1683 - microSD */
-&cp2_sdhci0 {
- status = "okay";
-};
-
-/* SLM-1521-V2, CON11 */
-&cp2_usb3_1 {
- status = "okay";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy3 1>;
-};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts
similarity index 54%
rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts
index 7dc6c6e..81ff188 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts
@@ -1,35 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * copyright (c) 2019 marvell international ltd.
+ * Copyright (C) 2019 Marvell International Ltd.
*
- * spdx-license-identifier: gpl-2.0
- * https://spdx.org/licenses
+ * Device tree for the CN9132-DB board.
*/
-#undef CP110_NUM
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
-#undef CP110_PCIEx_CPU_MEM_BASE
-#undef CP110_PCIEx_MEM_BASE
-
-/* CP110-1 Settings */
-#define CP110_NAME cp2
-#define CP110_NUM 2
-#define CP110_BASE f6000000
-#define CP110_PCIE0_BASE f6600000
-#define CP110_PCIE1_BASE f6620000
-#define CP110_PCIE2_BASE f6640000
-#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
-#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
-
-#include "armada-cp110.dtsi"
+#include "cn9131-db.dts"
/ {
- model = "DB-CN-9132";
- compatible = "marvell,cn9132", "marvell,armada-ap807-quad",
- "marvell,armada-ap807";
+ model = "Marvell Armada CN9132-DB";
+ compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ gpio5 = &cp2_gpio1;
+ gpio6 = &cp2_gpio2;
+ ethernet5 = &cp2_eth0;
+ };
cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
compatible = "regulator-fixed";
@@ -71,16 +58,57 @@
cp2_sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp2_sfpp0_i2c>;
- los-gpio = <&cp2_moudle_expander1 11 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&cp2_moudle_expander1 10 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&cp2_moudle_expander1 9 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&cp2_moudle_expander1 8 GPIO_ACTIVE_HIGH>;
+ los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the
I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
status = "disabled";
};
};
+/*
+ * Instantiate the second slave CP115
+ */
+
+#define CP11X_NAME cp2
+#define CP11X_BASE f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f6600000
+#define CP11X_PCIE1_BASE f6620000
+#define CP11X_PCIE2_BASE f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
&cp2_crypto {
+ status = "disabled";
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp2_eth0 {
status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp2_sfp_eth0>;
};
&cp2_gpio1 {
@@ -111,7 +139,7 @@
#size-cells = <0>;
reg = <1>;
/* U12 */
- cp2_moudle_expander1: pca9555@21 {
+ cp2_module_expander1: pca9555@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
@@ -122,7 +150,38 @@
};
};
+/* SLM-1521-V2, CON6 */
+&cp2_pcie0 {
+ status = "okay";
+ num-lanes = <2>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy0 0
+ &cp2_comphy1 0>;
+};
+
+/* SLM-1521-V2, CON8 */
+&cp2_pcie2 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy5 2>;
+};
+
+&cp2_sata0 {
+ status = "okay";
+
+ /* SLM-1521-V2, CON4 */
+ sata-port@0 {
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy2 0>;
+ };
+};
+
+/* CON 2 on SLM-1683 - microSD */
&cp2_sdhci0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp2_sdhci_pins>;
bus-width = <4>;
@@ -132,7 +191,7 @@
&cp2_syscon0 {
cp2_pinctrl: pinctrl {
- compatible = "marvell,armada-7k-pinctrl";
+ compatible = "marvell,cp115-standalone-pinctrl";
cp2_i2c0_pins: cp2-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
@@ -152,8 +211,11 @@
phy-names = "usb";
};
+/* SLM-1521-V2, CON11 */
&cp2_usb3_1 {
status = "okay";
usb-phy = <&cp2_usb3_0_phy1>;
phy-names = "usb";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy3 1>;
};
--
2.29.0
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