Hi Sami,
On Fri, Feb 12, 2021 at 5:28 PM Sami Mujawar <sami.muja...@arm.com> wrote:
>
> Hi Vijay,
>
> This patch needs similar changes as patch 2/3.
Ack.
>
> Regards,
>
> Sami Mujawar
>
> -----Original Message-----
> From: Vijayenthiran Subramaniam <vijayenthiran.subraman...@arm.com>
> Sent: 03 February 2021 09:07 AM
> To: devel@edk2.groups.io; jonathan.came...@huawei.com; l...@nuviainc.com;
> ardb+tianoc...@kernel.org; Sami Mujawar <sami.muja...@arm.com>
> Cc: Thomas Abraham <thomas.abra...@arm.com>
> Subject: [edk2-platforms] [PATCH v2 3/3] Platform/ARM/SgiPkg: Add HMAT ACPI
> table for RD-V1-MC
>
> Add HMAT ACPI tables that is specific for RD-V1-MC quad-chip platform.
> The latencies mentioned in the table are hypothetical values and
> represents typical latency between four chips. These values are
> applicable only for RD-V1-MC quad-chip fixed virtual and should not be
> reused for other platforms.
>
> Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subraman...@arm.com>
> ---
> Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
> Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 144
> ++++++++++++++++++++
> 2 files changed, 145 insertions(+)
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
> b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
> index 051825993af0..f3552bc49003 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
> @@ -22,6 +22,7 @@ [Sources]
> Iort.aslc
> Mcfg.aslc
> RdV1Mc/Dsdt.asl
> + RdV1Mc/Hmat.aslc
> RdV1Mc/Madt.aslc
> RdV1Mc/Srat.aslc
> Spcr.aslc
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
> b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
> new file mode 100644
> index 000000000000..d2c067d70be9
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
> @@ -0,0 +1,144 @@
> +/** @file
> +* Heterogeneous Memory Attribute Table (HMAT)
> +*
> +* Copyright (c) 2020, ARM Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include "SgiAcpiHeader.h"
> +#include "SgiPlatform.h"
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +
> +#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
> +#define INITATOR_PROXIMITY_DOMAIN_CNT 4
> +#define TARGET_PROXIMITY_DOMAIN_CNT 4
> +
> +//
> +// HMAT Table
> +//
> +#pragma pack (1)
> +
> +typedef struct {
> + UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
> + UINT32 TargetProximityDomain[TARGET_PROXIMITY_DOMAIN_CNT];
> + UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT *
> TARGET_PROXIMITY_DOMAIN_CNT];
> +} InitiatorTargetProximityMatrix;
> +
> +typedef struct {
> + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
> Header;
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
> Proximity[CHIP_CNT];
> + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
> LatencyInfo;
> + InitiatorTargetProximityMatrix
> Matrix;
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
> MemSideCache0;
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
> MemSideCache1;
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
> MemSideCache2;
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
> MemSideCache3;
> +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
> +
> +#pragma pack ()
> +
> +#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT(
> \
> + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy,
> CacheLineSize \
> + )
> \
> +{
> \
> + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy,
> CacheLineSize \
> +}
> +
> +EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
> + // Header
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
> + EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
> + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
> + ),
> + {
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE
> + },
> + },
> +
> + // Memory Proximity Domain
> + {
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> + 1, 0x0, 0x0),
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> + 1, 0x1, 0x1),
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> + 1, 0x2, 0x2),
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> + 1, 0x3, 0x3),
> + },
> +
> + // Latency Info
> +
> EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
> + 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
> + {
> + {0, 1, 2, 3}, {0, 1, 2, 3},
> + {
> + //
> + // The latencies mentioned in this table are hypothetical values and
> + // represents typical latency between four chips. These values are
> + // applicable only for RD-V1-MC quad-chip fixed virtual platform and
> + // should not be reused for other platforms.
> + //
> + 10, 20, 20, 20,
> + 20, 10, 20, 20,
> + 20, 20, 10, 20,
> + 20, 20, 20, 10,
> + }
> + },
> +
> + // Memory Side Cache
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> + 0x0, SIZE_1GB,
> + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> + 1,
> + 1,
> + 2,
> + 2,
> + 64 // 64 bytes cache line length
> + ),
> + 0),
> +
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> + 0x1, SIZE_1GB,
> + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> + 1,
> + 1,
> + 2,
> + 2,
> + 64 // 64 bytes cache line length
> + ),
> + 0),
> +
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> + 0x2, SIZE_1GB,
> + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> + 1,
> + 1,
> + 2,
> + 2,
> + 64 // 64 bytes cache line length
> + ),
> + 0),
> +
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> + 0x3, SIZE_1GB,
> + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> + 1,
> + 1,
> + 2,
> + 2,
> + 64 // 64 bytes cache line length
> + ),
> + 0),
> +};
> +
> +VOID* CONST ReferenceAcpiTable = &Hmat;
> --
> 2.17.1
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