Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com> > -----Original Message----- > From: Luo, Heng <heng....@intel.com> > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaga...@intel.com>; Desimone, > Nathaniel L <nathaniel.l.desim...@intel.com> > Subject: [PATCH 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 > > Adds the following files: > * IpBlock/Psf/IncludePrivate > * IpBlock/Psf/LibraryPrivate > > Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> > Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> > Signed-off-by: Heng Luo <heng....@intel.com> > --- > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib.h > | 520 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeSm > mPsfLibVer2.inf | 40 ++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib.c > | 203 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++ > > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibInte > rnal.h | 470 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ > > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibVer > 2.c | 115 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 1348 insertions(+) > > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib. > h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib. > h > new file mode 100644 > index 0000000000..f333be48d2 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLib. > h > @@ -0,0 +1,520 @@ > +/** @file > > + Header file for PchPsfPrivateLib. > > + > > + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > +**/ > > +#ifndef _PCH_PSF_PRIVATE_LIB_H_ > > +#define _PCH_PSF_PRIVATE_LIB_H_ > > + > > +#include <Library/PchPcrLib.h> > > +#include <Register/PchPcrRegs.h> > > + > > +typedef struct { > > + UINT32 Id; > > + PCH_SBI_PID SbPid; > > +} PSF_SEGMENT; > > + > > +/** > > + Get list of supported PSF segments. > > + > > + @param[out] PsfTable Array of supported PSF segments > > + @param[out] PsfTableLength Length of PsfTable > > +**/ > > +VOID > > +PsfSegments ( > > + OUT PSF_SEGMENT **PsfTable, > > + OUT UINT32 *PsfTableLength > > + ); > > + > > +// > > +// Structure for storing data on both PSF SideBand Port ID and > > +// PSF port register offset for specific device > > +// > > +typedef struct { > > + PCH_SBI_PID PsfPid; > > + UINT16 RegBase; > > +} PSF_PORT; > > + > > +/** > > + Disable device at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfDisableDevice ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Enable device at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfEnableDevice ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Hide PciCfgSpace of device at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfHideDevice ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Unhide PciCfgSpace of device at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfUnhideDevice ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Disable device BARs at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > + @param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,... > > + Mask corresponds to 32bit wide BARs > > +**/ > > +VOID > > +PsfDisableDeviceBar ( > > + IN PSF_PORT PsfPort, > > + IN UINT32 BarDisMask > > + ); > > + > > +/** > > + Enable device BARs at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > + @param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,... > > + Mask corresponds to 32bit wide BARs > > +**/ > > +VOID > > +PsfEnableDeviceBar ( > > + IN PSF_PORT PsfPort, > > + IN UINT32 BarEnMask > > + ); > > + > > +/** > > + Disable IDER device at PSF level > > +**/ > > +VOID > > +PsfDisableIderDevice ( > > + VOID > > + ); > > + > > +/** > > + Enable SOL device at PSF level > > +**/ > > +VOID > > +PsfEnableSolDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable SOL device at PSF level > > +**/ > > +VOID > > +PsfDisableSolDevice ( > > + VOID > > + ); > > + > > +/** > > + Set PMC ABASE value in PSF > > + > > + @param[in] Address Address for ACPI base. > > +**/ > > +VOID > > +PsfSetPmcAbase ( > > + IN UINT16 Address > > + ); > > + > > +/** > > + Get PMC ABASE value from PSF > > + > > + @retval Address Address for ACPI base. > > +**/ > > +UINT16 > > +PsfGetPmcAbase ( > > + VOID > > + ); > > + > > +/** > > + Get PMC PWRMBASE value from PSF > > + > > + @retval Address Address for PWRM base. > > +**/ > > +UINT32 > > +PsfGetPmcPwrmBase ( > > + VOID > > + ); > > + > > +/** > > + Hide Cnvi WiFi device's PciCfgSpace at PSF level > > +**/ > > +VOID > > +PsfHideCnviWifiDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable Cnvi Wifi device at PSF level > > +**/ > > +VOID > > +PsfDisableCnviWifiDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable HDAudio device at PSF level > > +**/ > > +VOID > > +PsfDisableHdaDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable Dsp bar at PSF level > > +**/ > > +VOID > > +PsfDisableDspBar ( > > + VOID > > + ); > > + > > +/** > > + Disable THC device at PSF level > > + > > + @param[in] ThcNumber Touch Host Controller Number THC0 or > THC1 > > +**/ > > +VOID > > +PsfDisableThcDevice ( > > + IN UINT32 ThcNumber > > + ); > > + > > +/** > > + Disable xDCI device at PSF level > > +**/ > > +VOID > > +PsfDisableXdciDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable xHCI device at PSF level > > +**/ > > +VOID > > +PsfDisableXhciDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable xHCI VTIO Phantom device at PSF level > > +**/ > > +VOID > > +PsfDisableXhciVtioDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable SATA device at PSF level > > + > > + @param[in] SataCtrlIndex SATA controller index > > +**/ > > +VOID > > +PsfDisableSataDevice ( > > + IN UINT32 SataCtrlIndex > > + ); > > + > > +/** > > + Return PSF_PORT for SCS eMMC device > > + > > + @retval PsfPort PSF PORT structure for SCS eMMC device > > +**/ > > +PSF_PORT > > +PsfScsEmmcPort ( > > + VOID > > + ); > > + > > +/** > > + Return PSF_PORT for SCS SD Card device > > + > > + @retval PsfPort PSF PORT structure for SCS SD Card device > > +**/ > > +PSF_PORT > > +PsfScsSdCardPort ( > > + VOID > > + ); > > + > > +/** > > + Return PSF_PORT for SCS UFS device > > + > > + @param[in] UfsNum UFS Device > > + > > + @retval PsfPort PSF PORT structure for SCS UFS device > > +**/ > > +PSF_PORT > > +PsfScsUfsPort ( > > + IN UINT32 UfsNum > > + ); > > + > > +/** > > + Disable ISH device at PSF level > > +**/ > > +VOID > > +PsfDisableIshDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable FPAK device at PSF level > > +**/ > > +VOID > > +PsfDisableFpakDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable ISH BAR1 at PSF level > > +**/ > > +VOID > > +PsfDisableIshBar1 ( > > + VOID > > + ); > > + > > +/** > > + Disable GbE device at PSF level > > +**/ > > +VOID > > +PsfDisableGbeDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable SMBUS device at PSF level > > +**/ > > +VOID > > +PsfDisableSmbusDevice ( > > + VOID > > + ); > > + > > +/** > > + Disable TraceHub ACPI devices at PSF level > > +**/ > > +VOID > > +PsfDisableTraceHubAcpiDevice ( > > + VOID > > + ); > > + > > +/** > > + Hide TraceHub ACPI devices PciCfgSpace at PSF level > > +**/ > > +VOID > > +PsfHideTraceHubAcpiDevice ( > > + VOID > > + ); > > + > > +/** > > + This procedure will hide TraceHub PciCfgSpace at PSF level > > +**/ > > +VOID > > +PsfHideTraceHubDevice ( > > + VOID > > + ); > > + > > +/** > > + This procedure will unhide TraceHub PciCfgSpace at PSF level > > +**/ > > +VOID > > +PsfUnhideTraceHubDevice ( > > + VOID > > + ); > > + > > +/** > > + This procedure will disable TraceHub device at PSF level > > +**/ > > +VOID > > +PsfDisableTraceHubDevice ( > > + VOID > > + ); > > + > > +/** > > + Configures rootspace 3 bus number for PCIe IMR use > > + > > + @param[in] Rs3Bus bus number > > +**/ > > +VOID > > +PsfSetRs3Bus ( > > + UINT8 Rs3Bus > > + ); > > + > > +/** > > + Disable PCIe Root Port at PSF level > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > +**/ > > +VOID > > +PsfDisablePcieRootPort ( > > + IN UINT32 RpIndex > > + ); > > + > > +/** > > + Program PSF grant counts for SATA > > + Call this before SATA ports are accessed for enumeration > > +**/ > > +VOID > > +PsfConfigureSataGrantCounts ( > > + VOID > > + ); > > + > > +/** > > + Specifies the root port configuration of the > > + PCIe controller. The number on the left of x > > + signifies the number of root ports in the controller > > + while value on the right is link width. N stands for > > + the number of PCIe lanes per root port instance. > > +**/ > > +typedef enum { > > + PsfPcieCtrl4xn, > > + PsfPcieCtrl1x2n_2xn, > > + PsfPcieCtrl2xn_1x2n, > > + PsfPcieCtrl2x2n, > > + PsfPcieCtrl1x4n, > > + PsfPcieCtrlUndefined > > +} PSF_PCIE_CTRL_CONFIG; > > + > > +/** > > + Program PSF grant counts for PCI express depending on controllers > configuration > > + > > + @param[in] PsfPcieCtrlConfigTable Table with PCIe controllers > configuration > > + @param[in] NumberOfPcieControllers Number of PCIe controllers. This is > also the size of PsfPcieCtrlConfig table > > +**/ > > +VOID > > +PsfConfigurePcieGrantCounts ( > > + IN PSF_PCIE_CTRL_CONFIG *PsfPcieCtrlConfigTable, > > + IN UINT32 NumberOfPcieControllers > > + ); > > + > > + > > +/** > > + This function enables EOI message forwarding in PSF for PCIe ports > > + for cases where IOAPIC is present behind this root port. > > + > > + @param[in] RpIndex Root port index (0 based) > > + > > + @retval Status > > +**/ > > +EFI_STATUS > > +PsfConfigurEoiForPciePort ( > > + IN UINT32 RpIndex > > + ); > > + > > +// > > +// Structure for PSF Port Destination ID > > +// > > +typedef union { > > + UINT32 RegVal; > > + struct { > > + UINT32 ChannelId : 8; // Channel ID > > + UINT32 PortId : 7; // Port ID > > + UINT32 PortGroupId : 1; // Port Group ID > > + UINT32 PsfId : 8; // PSF ID > > + UINT32 Rsvd : 7; // Reserved > > + UINT32 ChanMap : 1; // Channel map > > + } Fields; > > +} PSF_PORT_DEST_ID; > > + > > +/** > > + PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id) > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval Destination ID > > +**/ > > +PSF_PORT_DEST_ID > > +PsfPcieDestinationId ( > > + IN UINT32 RpIndex > > + ); > > + > > +/** > > + PSF early initialization. > > +**/ > > +VOID > > +PsfEarlyInit ( > > + VOID > > + ); > > + > > +/** > > + Assign new function number for PCIe Port Number. > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + @param[in] NewFunction New Function number > > +**/ > > +VOID > > +PsfSetPcieFunction ( > > + IN UINT32 RpIndex, > > + IN UINT32 NewFunction > > + ); > > + > > +/** > > + This function enables PCIe Relaxed Order in PSF > > +**/ > > +VOID > > +PsfEnablePcieRelaxedOrder ( > > + VOID > > + ); > > + > > + > > +/** > > + Enable VTd support in PSF. > > +**/ > > +VOID > > +PchPsfEnableVtd ( > > + VOID > > + ); > > + > > +/** > > + Disable PSF address-based peer-to-peer decoding. > > +**/ > > +VOID > > +PchPsfDisableP2pDecoding ( > > + VOID > > + ); > > + > > +/** > > + This procedure will hide PMC device at PSF level > > +**/ > > +VOID > > +PsfHidePmcDevice ( > > + VOID > > + ); > > + > > +/** > > + This procedure will disable D3:F0 device at PSF level for PCH-LP > > +**/ > > +VOID > > +PsfDisableD3F0 ( > > + VOID > > + ); > > + > > +/** > > + This procedure will disable PSF upstream completion tracking for HDAudio > on PCH-LP > > +**/ > > +VOID > > +PsfDisableUpstreamCompletionTrackingForHda ( > > + VOID > > + ); > > + > > +#endif // _PCH_PSF_PRIVATE_LIB_H_ > > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeS > mmPsfLibVer2.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeS > mmPsfLibVer2.inf > new file mode 100644 > index 0000000000..d8fc52444a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeS > mmPsfLibVer2.inf > @@ -0,0 +1,40 @@ > +## @file > > +# PEI/DXE/SMM PCH PSF Private Lib for TigerLake PCH > > +# > > +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > +# > > +## > > + > > +[Defines] > > +INF_VERSION = 0x00010017 > > +BASE_NAME = PeiDxeSmmPsfLibTgl > > +FILE_GUID = 28B03D2C-6FD5-4061-96B8-39E3F0402DE5 > > +VERSION_STRING = 1.0 > > +MODULE_TYPE = BASE > > +LIBRARY_CLASS = PsfLib > > +# > > +# The following information is for reference only and not required by the > build tools. > > +# > > +# VALID_ARCHITECTURES = IA32 X64 > > +# > > + > > +[LibraryClasses] > > + BaseLib > > + IoLib > > + DebugLib > > + PciSegmentLib > > + PchInfoLib > > + PchPcrLib > > + SataLib > > + CpuPcieInfoFruLib > > + PchPciBdfLib > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + TigerlakeSiliconPkg/SiPkg.dec > > + > > + > > +[Sources] > > + PsfLib.c > > + PsfLibVer2.c > > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib.c > new file mode 100644 > index 0000000000..1f0b11c11a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib.c > @@ -0,0 +1,203 @@ > +/** @file > > + This file contains PSF routines for RC usage > > + > > + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > +**/ > > +#include <Uefi/UefiBaseType.h> > > +#include <Library/IoLib.h> > > +#include <Library/DebugLib.h> > > +#include <Library/BaseMemoryLib.h> > > +#include <Library/PchPcrLib.h> > > +#include <Library/PchInfoLib.h> > > +#include <Library/SataLib.h> > > +#include <Library/CpuPcieInfoFruLib.h> > > +#include <Library/PsfLib.h> > > +#include <PchLimits.h> > > +#include <Register/PchRegsPsf.h> > > +#include <PchPcieRpInfo.h> > > +#include "PsfLibInternal.h" > > +#include <Library/PchPciBdfLib.h> > > + > > +/** > > + Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...) > > + > > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) > > + > > + @retval PSF SideBand Port ID > > +**/ > > +PCH_SBI_PID > > +PsfSbPortId ( > > + UINT32 PsfId > > + ) > > +{ > > + UINT32 PsfTableIndex; > > + PSF_SEGMENT *PsfTable; > > + UINT32 PsfTableSize; > > + > > + PsfSegments (&PsfTable, &PsfTableSize); > > + > > + for (PsfTableIndex = 0; PsfTableIndex < PsfTableSize; PsfTableIndex++) { > > + if (PsfTable[PsfTableIndex].Id == PsfId) { > > + return PsfTable[PsfTableIndex].SbPid; > > + } > > + } > > + > > + ASSERT (FALSE); > > + return 0; > > +} > > + > > + > > +/** > > + Get PCH Root PSF ID. This is the PSF segment to which OPDMI/DMI is > connected. > > + > > + @retval PsfId Root PSF ID > > +**/ > > +UINT32 > > +PsfRootId ( > > + VOID > > + ) > > +{ > > + PSF_SEGMENT *PsfTable; > > + UINT32 PsfTableSize; > > + > > + PsfSegments (&PsfTable, &PsfTableSize); > > + > > + return PsfTable[0].Id; > > +} > > + > > +/** > > + Add EOI Target in a given PSF > > + > > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) > > + @param[in] TargetId EOI Target ID > > +**/ > > +STATIC > > +VOID > > +PsfAddEoiTarget ( > > + UINT32 PsfId, > > + PSF_PORT_DEST_ID TargetId > > + ) > > +{ > > + UINT16 EoiTargetBase; > > + UINT16 EoiControlBase; > > + UINT8 NumOfEnabledTargets; > > + UINT8 MaximalNumberOfTargets; > > + PCH_SBI_PID PsfSbiPortId; > > + UINT32 Data32; > > + UINT8 TargetIndex; > > + > > + MaximalNumberOfTargets = PsfEoiRegData (PsfId, &EoiTargetBase, > &EoiControlBase); > > + PsfSbiPortId = PsfSbPortId (PsfId); > > + > > + // > > + // Get number of enabled agents from > PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI register > > + // > > + Data32 = PchPcrRead32 (PsfSbiPortId, EoiControlBase); > > + NumOfEnabledTargets = (UINT8) (Data32 >> > N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC); > > + > > + // > > + // Check if target was not already enabled > > + // Targets from a different PSF segment are aggregated into single > destination on > > + // current PSF segment. > > + // > > + for (TargetIndex = 0; TargetIndex < NumOfEnabledTargets; > TargetIndex++) { > > + Data32 = PchPcrRead32 (PsfSbiPortId, EoiTargetBase + TargetIndex * 4); > > + // > > + // If target already added don't add it again > > + // > > + if (Data32 == TargetId.RegVal) { > > + ASSERT (FALSE); > > + return; > > + } > > + // > > + // If target is from different PSF segment than currently being analyzed > > + // it is enough that its PsfID is matching > > + // > > + if ((Data32 & B_PCH_PSFX_PCR_TARGET_PSFID) >> > N_PCH_PSFX_PCR_TARGET_PSFID == TargetId.Fields.PsfId) { > > + return; > > + } > > + } > > + > > + // > > + // Check if next one can be added > > + // > > + if (NumOfEnabledTargets >= MaximalNumberOfTargets) { > > + ASSERT (FALSE); > > + return; > > + } > > + > > + // > > + // Add next target > > + // Configure Multicast Destination ID register with target device on PSF. > > + // Configuration must be done in next available > PSF_MC_AGENT_MCAST0_RS0_TGT<x>_EOI register > > + // so that other targets are not overridden. <x> is known from the > number of multicast agents > > + // in Multicast Control Register. Value programmed is based on > > + // PsfID, PortGroupID, PortID and ChannelID of the target > > + // > > + PchPcrWrite32 (PsfSbiPortId, EoiTargetBase + NumOfEnabledTargets * 4, > TargetId.RegVal); > > + > > + // > > + // Enable new target > > + // Configure PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI, increase > NumMc and set MultCEn > > + // > > + NumOfEnabledTargets++; > > + Data32 = (NumOfEnabledTargets << > N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC) | > B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN; > > + PchPcrWrite32 (PsfSbiPortId, EoiControlBase, Data32); > > +} > > + > > +/** > > + Enable EOI Target > > + > > + @param[in] TargetId Target ID > > +**/ > > +STATIC > > +VOID > > +PsfEnableEoiTarget ( > > + PSF_PORT_DEST_ID TargetId > > + ) > > +{ > > + UINT32 RootLevelPsf; > > + > > + RootLevelPsf = PsfRootId (); > > + > > + // > > + // Enable EOI target in root PSF > > + // > > + PsfAddEoiTarget (RootLevelPsf, TargetId); > > + > > + // > > + // Enable EOI target on other PSF segment if target > > + // is not located on root PSF > > + // > > + if (TargetId.Fields.PsfId != RootLevelPsf) { > > + PsfAddEoiTarget (TargetId.Fields.PsfId, TargetId); > > + } > > +} > > + > > +/** > > + This function enables EOI message forwarding in PSF for PCIe ports > > + for cases where IOAPIC is present behind this root port. > > + > > + @param[in] RpIndex Root port index (0 based) > > + > > + @retval Status > > +**/ > > +EFI_STATUS > > +PsfConfigurEoiForPciePort ( > > + IN UINT32 RpIndex > > + ) > > +{ > > + ASSERT (RpIndex < GetPchMaxPciePortNum ()); > > + > > + // > > + // If there is an IOAPIC discovered behind root port program PSF Multicast > registers > > + // accordingly to CNL PCH BWG PSF EOI Multicast Configuration > > + // Since there is a device behind RootPort to which EOI needs to be > forwarded > > + // enable multicast (MULTCEN) and increase the number of multicast > agents (NUMMC) > > + // in Multicast Control Register. > > + // > > + PsfEnableEoiTarget (PsfPcieDestinationId (RpIndex)); > > + > > + return EFI_SUCCESS; > > +} > > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibIn > ternal.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibIn > ternal.h > new file mode 100644 > index 0000000000..9d636b5298 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibIn > ternal.h > @@ -0,0 +1,470 @@ > +/** @file > > + This file contains internal header for PSF lib usage > > + > > + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > +**/ > > +#ifndef _PCH_PSF_PRIVATE_LIB_INTERNAL_H_ > > +#define _PCH_PSF_PRIVATE_LIB_INTERNAL_H_ > > + > > +#include <Library/PsfLib.h> > > +#include <Register/PchPcrRegs.h> > > + > > +#define PSF_PORT_NULL ((PSF_PORT){0,0}) > > +#define PSF_IS_PORT_NULL(PsfPort) ((PsfPort.PsfPid == 0) && > (PsfPort.RegBase == 0)) > > + > > +typedef struct { > > + PCH_SBI_PID PsfPid; > > + UINT32 RegisterAddress; > > + UINT8 Fro; > > +} PSF_PORT_RELAXED_ORDERING_CONFIG_REG; > > +/** > > + Disable bridge (e.g. PCIe Root Port) at PSF level > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfDisableBridge ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Disable bridge (e.g. PCIe Root Port) at PSF level in RS3 > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfRs3DisableBridge ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Check if bridge (e.g. PCIe Root Port) is enabled at PSF level > > + > > + @param[in] PsfPort PSF PORT data structure > > + > > + @retval TRUE Bridge behind PSF Port is enabled > > + FALSE Bridge behind PSF Port is disabled > > +**/ > > +BOOLEAN > > +PsfIsBridgeEnabled ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Disable device IOSpace at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfDisableDeviceIoSpace ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Enable device IOSpace at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfEnableDeviceIoSpace ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Disable device Memory Space at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfDisableDeviceMemSpace ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Enable device Memory Space at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > +**/ > > +VOID > > +PsfEnableDeviceMemSpace ( > > + IN PSF_PORT PsfPort > > + ); > > + > > +/** > > + Set device BARx address at PSF level > > + Method not for bridges (e.g. PCIe Root Port) > > + > > + @param[in] PsfPort PSF PORT data structure > > + @param[in] BarNum BAR Number (0:BAR0, 1:BAR1, ...) > > + @param[in] BarValue 32bit BAR value > > +**/ > > +VOID > > +PsfSetDeviceBarValue ( > > + IN PSF_PORT PsfPort, > > + IN UINT8 BarNum, > > + IN UINT32 BarValue > > + ); > > + > > +/** > > + Return PSF_PORT for TraceHub device > > + > > + @retval PsfPort PSF PORT structure for TraceHub device > > +**/ > > +PSF_PORT > > +PsfTraceHubPort ( > > + VOID > > + ); > > + > > +/** > > + This procedure will return PSF_PORT for TraceHub ACPI device > > + > > + @retval PsfPort PSF PORT structure for TraceHub ACPI device > > +**/ > > +PSF_PORT > > +PsfTraceHubAcpiDevPort ( > > + VOID > > + ); > > + > > +/** > > + This procedure will return PSF_PORT for SOL device > > + > > + @retval PsfPort PSF PORT structure for SOL device > > +**/ > > +PSF_PORT > > +PsfSolPort ( > > + VOID > > + ); > > + > > +/** > > + Return PSF_PORT for ISH device > > + > > + @retval PsfPort PSF PORT structure for ISH device > > +**/ > > +PSF_PORT > > +PsfIshPort ( > > + VOID > > + ); > > + > > +/** > > + Return PSF_PORT for FPAK device > > + > > + @retval PsfPort PSF PORT structure for FPAK device > > +**/ > > +PSF_PORT > > +PsfFpakPort ( > > + VOID > > + ); > > + > > +/** > > + Return PSF_PORT for CNVi device > > + > > + @retval PsfPort PSF PORT structure for CNVi device > > +**/ > > +PSF_PORT > > +PsfCnviPort ( > > + VOID > > + ); > > + > > +/** > > + Return PSF_PORT for PMC device > > + > > + @retval PsfPort PSF PORT structure for PMC device > > +**/ > > +PSF_PORT > > +PsfPmcPort ( > > + VOID > > + ); > > + > > +/** > > + Return second level PSF_PORT to which PCIE Root Port device is connected > (directly) > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval PsfPort PSF PORT structure for PCIe > > +**/ > > +PSF_PORT > > +PsfPcieSecondLevelPort ( > > + IN UINT32 RpIndex > > + ); > > + > > +/** > > + Return PSF_PORT at root PSF level to which PCIe Root Port device is > connected > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval PsfPort PSF PORT structure for PCIe > > + > > +**/ > > +PSF_PORT > > +PsfRootPciePort ( > > + IN UINT32 RpIndex > > + ); > > + > > +/** > > + Return RS3 PSF_PORT at root PSF level to which PCIe Root Port device is > connected > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval PsfPort PSF PORT structure for PCIe > > +**/ > > +PSF_PORT > > +PsfRootRs3PciePort ( > > + IN UINT32 RpIndex > > + ); > > + > > +/** > > + Check if PCIe Root Port is enabled > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval TRUE PCIe Root Port is enabled > > + FALSE PCIe Root Port is disabled > > +**/ > > +BOOLEAN > > +PsfIsPcieRootPortEnabled ( > > + IN UINT32 RpIndex > > + ); > > + > > +// > > +// Type of enpoint connected to PSF port. > > +// PsfNullPort is used for ports which do not exist > > +// > > +typedef enum { > > + PsfNullPort, > > + PsfToPsfPort, > > + PsfPcieCtrlPort > > +} PSF_TOPO_PORT_TYPE; > > + > > +// > > +// Structure for storing information on location in PSF topology > > +// Every PSF node is identified by PsfID and PsfPortId > > +// > > +typedef struct { > > + UINT8 PsfId; > > + UINT8 PortId; > > +} PSF_TOPO_PORT; > > + > > +#define PSF_TOPO_PORT_NULL ((PSF_TOPO_PORT){0, 0}) > > +#define PSF_IS_TOPO_PORT_NULL(PsfTopoPort) (((PsfTopoPort).PsfId == > 0) && ((PsfTopoPort).PortId == 0)) > > + > > +// > > +// This is optional field containing PSF port specific data > > +// > > +typedef union { > > + UINT32 PcieCtrlIndex; > > +} PSF_TOPO_PORT_DATA; > > + > > +// > > +// Structure representing PSF port in PSF topology > > +// If port is of PsfToPsfPort type Child will point to the first > > +// port of sub PSF segment. > > +// > > +typedef struct PSF_TOPOLOGY { > > + PSF_TOPO_PORT PsfPort; > > + PSF_TOPO_PORT_TYPE PortType; > > + CONST struct PSF_TOPOLOGY *Child; > > + PSF_TOPO_PORT_DATA PortData; > > +} PSF_TOPOLOGY; > > + > > +// > > +// Tag for identifying last element of PSF_TOPOLOGY type array > > +// > > +#define PSF_TOPOLOGY_END {{0, 0}, PsfNullPort, NULL} > > + > > +/** > > + Get PSF Pcie Tree topology > > + > > + @param[in] PsfTopology PSF Port from PSF PCIe tree topology > > + > > + @retval PsfTopology PSF PCIe tree topology > > +**/ > > +CONST PSF_TOPOLOGY* > > +PsfGetRootPciePsfTopology ( > > + VOID > > + ); > > + > > +// > > +// Structure for storing data on PCIe controller to PSF assignment and > GrantCount register offsets > > +// > > +typedef struct { > > + PCH_SBI_PID PsfPid; > > + UINT16 DevGntCnt0Base; > > + UINT16 TargetGntCntPg1Tgt0Base; > > +} PSF_GRANT_COUNT_REG; > > + > > +/** > > + Grant count regs data for PSF that is directly connected to PCIe Root Ports > > + > > + @param[in] Controller PCIe Root Port Controller index (0 based) > > + @param[out] GrantCountReg Structure with PSF Grant Count register > data > > +**/ > > +VOID > > +PsfPcieGrantCountBaseReg ( > > + IN UINT8 Controller, > > + OUT PSF_GRANT_COUNT_REG *GrantCountReg > > + ); > > + > > +/** > > + Get Grant Count number (Device Grant Count and Target Grant Count) > > + for PSF that is directly connected to PCIe Root Ports > > + > > + @param[in] Controller PCIe Root Port Controller index > > + @param[in] Channel PCIe Root Port Channel index > > + @param[out] DgcrNo Device Grant Count number > > + @param[out] PgTgtNo Target Grant Count number > > +**/ > > +VOID > > +PsfPcieGrantCountNumber ( > > + IN UINT8 Controller, > > + IN UINT8 Channel, > > + OUT UINT8 *DgcrNo, > > + OUT UINT8 *PgTgtNo > > + ); > > + > > +/** > > + Grant count regs data for a given PSF-to-PSF port. > > + > > + @param[in] PsfTopoPort PSF-to-PSF port > > + > > + @param[out] GrantCountReg Structure with PSF Grant Count register > data > > +**/ > > +VOID > > +PsfSegmentGrantCountBaseReg ( > > + IN PSF_TOPO_PORT PsfTopoPort, > > + OUT PSF_GRANT_COUNT_REG *GrantCountReg > > + ); > > + > > +/** > > + Grant Count number (Device Grant Count and Target Grant Count) for a > given PSF-to-PSF port. > > + > > + @param[in] PsfTopoPort PSF-to-PSF port > > + @param[out] DgcrNo Device Grant Count number > > + @param[out] PgTgtNo Target Grant Count number > > +**/ > > +VOID > > +PsfSegmentGrantCountNumber ( > > + IN PSF_TOPO_PORT PsfTopoPort, > > + OUT UINT8 *DgcrNo, > > + OUT UINT8 *PgTgtNo > > + ); > > + > > +// > > +// Do not override PSF Grant Count value and leave HW default setting > > +// > > +#define DEFAULT_PCIE_GRANT_COUNT 0xFF > > + > > +/** > > + Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...) > > + > > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) > > + > > + @retval PSF SideBand Port ID > > +**/ > > +PCH_SBI_PID > > +PsfSbPortId ( > > + UINT32 PsfId > > + ); > > + > > +/** > > + Get EOI register data for given PSF ID > > + > > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) > > + @param[out] EoiTargetBase EOI Target register > > + @param[out] EoiControlBase EOI Control register > > + > > + @retval MaxTargets Number of supported targets > > + > > +**/ > > +UINT8 > > +PsfEoiRegData ( > > + UINT32 PsfId, > > + UINT16 *EoiTargetBase, > > + UINT16 *EoiControlBase > > + ); > > + > > +/** > > + Get MCTP register data for given PSF ID > > + > > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) > > + @param[out] MctpTargetBase MCTP Target register > > + @param[out] MctpControlBase MCTP Control register > > + > > + @retval MaxTargets Number of supported targets > > + > > +**/ > > +UINT8 > > +PsfMctpRegData ( > > + UINT32 PsfId, > > + UINT16 *MctpTargetBase, > > + UINT16 *MctpControlBase > > + ); > > + > > +/** > > + Check if MCTP is supported > > + > > + @retval TRUE MCTP is supported > > + FALSE MCTP is not supported > > +**/ > > +BOOLEAN > > +PsfIsMctpSupported ( > > + VOID > > + ); > > + > > +/** > > + Return the PSF (Root level) Function Config PSF_PORT for PCIe Root Port > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval PsfPort PSF PORT structure for PCIe Function Config > > +**/ > > +PSF_PORT > > +PsfRootPcieFunctionConfigPort ( > > + IN UINT32 RpIndex > > + ); > > + > > +/** > > + Return the PSF (Root level) RS3 Function Config PSF_PORT for PCIe Root > Port > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval PsfPort PSF PORT structure for PCIe Function Config > > +**/ > > +PSF_PORT > > +PsfRootRs3PcieFunctionConfigPort ( > > + IN UINT32 RpIndex > > + ); > > + > > +/** > > + Return the PSF Function Config Second Level PSF_PORT for PCIe Root Port > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval PsfPort PSF PORT structure for PCIe Function Config > > +**/ > > +PSF_PORT > > +PsfPcieFunctionConfigSecondLevelPort ( > > + IN UINT32 RpIndex > > + ); > > + > > +/** > > + This function returns Psf Port Relaxed Ordering Configs > > + > > + @param[out] PsfPortRelaxedOrderingConfigRegs PCH > Series > specific table > > + @param[out] PsfPortRelaxedOrderingConfigRegsTableSize PCH > Series specific table size > > + @param[out] PsfPortRelaxedOrderingConfigRegsPchTypeSpecific > PCH type specific table > > + @param[out] > PsfPortRelaxedOrderingConfigRegsPchTypeSpecificTableSize PCH type > specific table size > > +**/ > > +VOID > > +GetPsfPortRelaxedOrderingTables ( > > + PSF_PORT_RELAXED_ORDERING_CONFIG_REG** > PsfPortRelaxedOrderingConfigRegs, > > + UINT32* > PsfPortRelaxedOrderingConfigRegsTableSize, > > + PSF_PORT_RELAXED_ORDERING_CONFIG_REG** > PsfPortRelaxedOrderingConfigRegsPchTypeSpecific, > > + UINT32* > PsfPortRelaxedOrderingConfigRegsPchTypeSpecificTableSize > > + ); > > + > > +#endif > > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibV > er2.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibV > er2.c > new file mode 100644 > index 0000000000..fd21e5bed4 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLibV > er2.c > @@ -0,0 +1,115 @@ > +/** @file > > + This file contains internal PSF routines for PCH PSF VER2 lib usage > > + > > + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > +**/ > > +#include <Uefi/UefiBaseType.h> > > +#include <Library/IoLib.h> > > +#include <Library/DebugLib.h> > > +#include <Library/PchPcrLib.h> > > +#include <Library/PchInfoLib.h> > > +#include <Library/SataLib.h> > > +#include <Library/BaseMemoryLib.h> > > +#include <Register/PchRegsPsf.h> > > +#include "PsfLibInternal.h" > > +#include <PchPcieRpInfo.h> > > + > > + > > +/** > > + Get EOI register data for given PSF ID > > + > > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) > > + @param[out] EoiTargetBase EOI Target register > > + @param[out] EoiControlBase EOI Control register > > + > > + @retval MaxTargets Number of supported targets > > + > > +**/ > > +UINT8 > > +PsfEoiRegData ( > > + UINT32 PsfId, > > + UINT16 *EoiTargetBase, > > + UINT16 *EoiControlBase > > + ) > > +{ > > + UINT8 MaxTargets; > > + > > + MaxTargets = 0; > > + *EoiTargetBase = 0; > > + *EoiControlBase = 0; > > + > > + switch (PsfId) { > > + case 1: > > + break; > > + > > + case 3: > > + break; > > + > > + case 7: > > + break; > > + > > + case 8: > > + break; > > + > > + case 9: > > + break; > > + > > + default: > > + break; > > + > > + } > > + return MaxTargets; > > +} > > + > > +GLOBAL_REMOVE_IF_UNREFERENCED PSF_PORT_DEST_ID > PchLpRpDestId[] = > > +{ > > + {0x18000}, {0x18001}, {0x18002}, {0x18003}, // SPA: PSF1, PortID = 0 > > + {0x18100}, {0x18101}, {0x18102}, {0x18103}, // SPB: PSF1, PortID = 1 > > + {0x18200}, {0x18201}, {0x18202}, {0x18203}, // SPC: PSF1, PortID = 2 > > +}; > > + > > +/** > > + PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id) > > + > > + @param[in] RpIndex PCIe Root Port Index (0 based) > > + > > + @retval Destination ID > > +**/ > > +PSF_PORT_DEST_ID > > +PsfPcieDestinationId ( > > + IN UINT32 RpIndex > > + ) > > +{ > > + if (RpIndex < ARRAY_SIZE (PchLpRpDestId)) { > > + return PchLpRpDestId[RpIndex]; > > + } > > + ASSERT (FALSE); > > + return (PSF_PORT_DEST_ID){0}; > > +} > > + > > +GLOBAL_REMOVE_IF_UNREFERENCED PSF_SEGMENT mPchLpPsfTable[] = > > +{ > > + {1, PID_PSF1}, > > + {2, PID_PSF2}, > > + {3, PID_PSF3}, > > + {4, PID_PSF4}, > > + {5, PID_CSME_PSF}, > > + {6, PID_PSF6} > > +}; > > + > > +/** > > + Get list of supported PSF segments. > > + > > + @param[out] PsfTable Array of supported PSF segments > > + @param[out] PsfTableLength Length of PsfTable > > +**/ > > +VOID > > +PsfSegments ( > > + OUT PSF_SEGMENT **PsfTable, > > + OUT UINT32 *PsfTableLength > > + ) > > +{ > > +*PsfTable = mPchLpPsfTable; > > + *PsfTableLength = ARRAY_SIZE (mPchLpPsfTable); > > +} > > -- > 2.24.0.windows.2
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