Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com> > -----Original Message----- > From: Luo, Heng <heng....@intel.com> > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaga...@intel.com>; Desimone, > Nathaniel L <nathaniel.l.desim...@intel.com> > Subject: [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate > headers > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171 > > Adds the following header files: > * Fru/TglCpu/IncludePrivate > > Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> > Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> > Signed-off-by: Heng Luo <heng....@intel.com> > --- > > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFr > uLib.h | 18 ++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPci > eRegs.h | 24 ++++++++++++++++++++++++ > > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs > .h | 42 ++++++++++++++++++++++++++++++++++++++++++ > > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuReg > s.h | 31 +++++++++++++++++++++++++++++++ > > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdReg > s.h | 22 ++++++++++++++++++++++ > 5 files changed, 137 insertions(+) > > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInit > FruLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInit > FruLib.h > new file mode 100644 > index 0000000000..a46b29cbbe > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Librar > +++ y/VtdInitFruLib.h > @@ -0,0 +1,18 @@ > +/** @file+ Vtd Initialization Fru Library header file++ Copyright (c) 2021, > Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2- > Clause-Patent+**/+#ifndef _VTD_INIT_FRU_LIB_H_+#define > _VTD_INIT_FRU_LIB_H_++///+/// TCSS DMA controller RMRR buffer 4MB > for each DMA controller+///+#define RMRR_TCSS_DMA_SIZE > 0x400000++extern UINT16 mDevEnMap[][2];+extern UINTN > mDevEnMapSize;++#endif // _VTD_INIT_FRU_LIB_H_diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuP > cieRegs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuP > cieRegs.h > new file mode 100644 > index 0000000000..a571381202 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Regist > +++ er/CpuPcieRegs.h > @@ -0,0 +1,24 @@ > +/** @file+ This file contains definitions of PCIe Configuration++ > Copyright > (c) 2021, Intel Corporation. All rights reserved.<BR>+ SPDX-License- > Identifier: BSD-2-Clause-Patent+**/++#ifndef > _CPU_PCIE_REGS_H_+#define _CPU_PCIE_REGS_H_++#define > R_PCIE_LCAP 0x4C+#define R_PCIE_LCTL > 0x50+#define R_PCIE_LSTS 0x52+#define > R_PCIE_SLCAP > 0x54+#define R_PCIE_SLSTS 0x5A+#define > R_PCIE_LCTL2 > 0x70+#define R_PCIE_MPC 0xD8+#define > B_PCIE_MPC_HPME BIT1+#define R_PCIE_PGTHRES > 0x5C0+#define B_PCIE_PGTHRES_L1PGLTREN BIT0+#define > R_PCIE_LCTL3 0xA34+#define B_PCIE_LCTL3_PE > BIT0++#endifdiff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRe > gs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdR > egs.h > new file mode 100644 > index 0000000000..f0b30107f4 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Regist > +++ er/IgdRegs.h > @@ -0,0 +1,42 @@ > +/** @file+ Register names for IGD block+ <b>Conventions</b>:+ - > Prefixes:+ - Definitions beginning with "R_" are registers+ - > Definitions > beginning with "B_" are bits within registers+ - Definitions beginning with > "V_" are meaningful values of bits within the registers+ - Definitions > beginning with "S_" are register sizes+ - Definitions beginning with "N_" > are > the bit position+ - In general, SA registers are denoted by "_SA_" in > register > names+ - Registers / bits that are different between SA generations are > denoted by+ "_SA_[generation_name]_" in register/bit names. e.g., > "_SA_HSW_"+ - Registers / bits that are different between SKUs are > denoted by "_[SKU_name]"+ at the end of the register/bit names+ - > Registers / bits of new devices introduced in a SA generation will be just > named+ as "_SA_" without [generation_name] inserted.++ Copyright (c) > 2021, Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: > BSD-2-Clause-Patent+**/+#ifndef _IGD_REGS_H_+#define > _IGD_REGS_H_++///+/// Device 2 Register Equates+///+//+// The following > equates must be reviewed and revised when the specification is > ready.+//+#define IGD_BUS_NUM 0x00+#define IGD_DEV_NUM > 0x02+#define IGD_FUN_NUM 0x00++///+/// GTTMMADR aligned to > 16MB (Base address = [38:24])+///+#define R_SA_IGD_GTTMMADR > 0x10++#define R_SA_IGD_SWSCI_OFFSET 0x00E8+#define > R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage++#endifdiff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuR > egs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuR > egs.h > new file mode 100644 > index 0000000000..afc72e8db0 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Regist > +++ er/IpuRegs.h > @@ -0,0 +1,31 @@ > +/** @file+ Register names for IPU block+ <b>Conventions</b>:+ - > Prefixes:+ - Definitions beginning with "R_" are registers+ - > Definitions > beginning with "B_" are bits within registers+ - Definitions beginning with > "V_" are meaningful values of bits within the registers+ - Definitions > beginning with "S_" are register sizes+ - Definitions beginning with "N_" > are > the bit position+ - IPU registers are denoted by "_IPU_" in register names+ > - > Registers / bits that are different between IPU generations are denoted by+ > "_IPU_[generation_name]_" in register/bit names. e.g., "_IPU_TGL_"+ - > Registers / bits that are different between SKUs are denoted by > "_[SKU_name]"+ at the end of the register/bit names+ - Registers / bits of > new devices introduced in a IPU generation will be just named+ as "_IPU_" > without [generation_name] inserted.++ Copyright (c) 2021, Intel > Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2- > Clause-Patent+**/+#ifndef _IPU_REGS_H_+#define _IPU_REGS_H_++//+// > Device 5 Equates+//+#define IPU_BUS_NUM 0x00+#define > IPU_DEV_NUM 0x05+#define IPU_FUN_NUM 0x00++#endif // > _IPU_REGS_H_diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdR > egs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdR > egs.h > new file mode 100644 > index 0000000000..d796a44afc > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Regist > +++ er/VtdRegs.h > @@ -0,0 +1,22 @@ > +/** @file+ Register names for VTD block+ <b>Conventions</b>:+ - > Prefixes:+ - Definitions beginning with "R_" are registers+ - > Definitions > beginning with "B_" are bits within registers+ - Definitions beginning with > "V_" are meaningful values of bits within the registers+ - Definitions > beginning with "S_" are register sizes+ - Definitions beginning with "N_" > are > the bit position+ Copyright (c) 2021, Intel Corporation. All rights > reserved.<BR>+ SPDX-License-Identifier: BSD-2-Clause-Patent+**/+#ifndef > _VTD_REGS_H_+#define _VTD_REGS_H_++///+/// Vt-d Engine base > address.+///+#define R_MCHBAR_VTD1_OFFSET 0x5400 ///< HW > UNIT1 for IGD+#define R_MCHBAR_VTD3_OFFSET 0x5410 ///< HW > UNIT3 for all other - PEG, USB, SATA etc++#endif-- > 2.24.0.windows.2
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