REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files:
* IpBlock/CpuPcieRp/Include
* IpBlock/CpuPcieRp/IncludePrivate
* IpBlock/CpuPcieRp/Library
* IpBlock/CpuPcieRp/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Signed-off-by: Heng Luo <heng....@intel.com>
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
| 31
+++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h
| 353
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h
| 47
+++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Library/DxeCpuPcieRpLib.h
| 18 ++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/CpuPcieInitCommon.c
| 445
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf
| 33 +++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/CpuPcieRpLib.c
| 48
++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf
| 32 ++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c
| 62
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf
| 40 ++++++++++++++++++++++++++++++++++++++++
10 files changed, 1109 insertions(+)
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 0000000000..15eeab0ecf
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,31 @@
+/** @file
+ This file contains definitions of PCIe controller information
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX 5
+
+//
+// Device 1 Memory Mapped IO Register Offset Equates
+//
+#define SA_PEG_DEV_NUM 0x01
+#define SA_PEG0_DEV_NUM SA_PEG_DEV_NUM
+#define SA_PEG3_DEV_NUM 0x06
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+
+#define SA_PEG_MAX_FUN 0x04
+#define SA_PEG_MAX_LANE 0x14
+#define SA_PEG_MAX_FUN_GEN3 0x03
+#define SA_PEG_MAX_LANE_GEN3 0x10
+#define SA_PEG_MAX_BUNDLE_GEN3 0x08
+
+#endif
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h
new file mode 100644
index 0000000000..79b255c273
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieInitCommon.h
@@ -0,0 +1,353 @@
+/** @file
+Header file for CpuPcieInitCommonLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INIT_COMMON_H_
+#define _CPU_PCIE_INIT_COMMON_H_
+
+#include <Library/CpuRegbarAccessLib.h>
+
+/**
+ Print registers value
+
+ @param[in] PrintMmioBase Mmio base address
+ @param[in] PrintSize Number of registers
+ @param[in] OffsetFromBase Offset from mmio base address
+
+ @retval None
+**/
+VOID
+SaPrintRegisters (
+ IN UINTN PrintMmioBase,
+ IN UINT32 PrintSize,
+ IN UINT32 OffsetFromBase
+ );
+
+/**
+ Print registers value
+
+ @param[in] PrintPciSegmentBase Pci segment base address
+ @param[in] PrintSize Number of registers
+ @param[in] OffsetFromBase Offset from mmio base address
+
+ @retval None
+**/
+VOID
+SaPrintPciRegisters (
+ IN UINT64 PrintPciSegmentBase,
+ IN UINT32 PrintSize,
+ IN UINT32 OffsetFromBase
+ );
+
+//
+// 2LM: PegPcie APIs for Sideband Access Mechanism in 2LM mode
+//
+/**
+Reads an 8-bit PCI configuration register.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentRead8 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+
+@return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PegPciSegmentRead8 (
+ IN UINT64 Address
+ );
+
+/**
+Writes an 8-bit PCI configuration register.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentWrite8 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+@param Value The value to write.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PegPciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ );
+
+/**
+Reads a 16-bit PCI configuration register.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentRead16 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+
+@return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PegPciSegmentRead16 (
+ IN UINT64 Address
+ );
+
+/**
+Writes a 16-bit PCI configuration register.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentWrite16 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+@param Value The value to write.
+
+@return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PegPciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ );
+
+/**
+Reads a 32-bit PCI configuration register.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentRead32 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+
+@return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PegPciSegmentRead32 (
+ IN UINT64 Address
+ );
+
+/**
+Writes a 32-bit PCI configuration register.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentWrite32 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+@param Value The value to write.
+
+@return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PegPciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ );
+
+/**
+Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit
value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentOr16 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param OrData The value to OR with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+**/
+UINT16
+EFIAPI
+PegPciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ );
+
+/**
+Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentAnd32 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param AndData The value to AND with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PegPciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ );
+
+/**
+Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bit
value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentAnd8 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param AndData The value to AND with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PegPciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ );
+
+/**
+Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit
value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentOr32 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param OrData The value to OR with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PegPciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ );
+
+/**
+Performs a bitwise OR of a 8-bit PCI configuration register with a 8-bit value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentOr8 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param OrData The value to OR with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PegPciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ );
+
+/**
+Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentAnd32 function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param AndData The value to AND with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PegPciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ );
+
+/**
+Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
value,
+followed a bitwise OR with another 32-bit value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentAndThenOr32
function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param AndData The value to AND with the PCI configuration register.
+@param OrData The value to OR with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PegPciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
value,
+followed a bitwise OR with another 16-bit value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentAndThenOr16
function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param AndData The value to AND with the PCI configuration register.
+@param OrData The value to OR with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PegPciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bit
value,
+followed a bitwise OR with another 8-bit value.
+
+Its a wrapper library function. This function uses side band access for PEG60
when 2LM mode is enabled.
+Other calls to this function will be routed to core PciSegmentAndThenOr8
function.
+
+@param Address Address that encodes the PCI Segment, Bus, Device, Function,
and Register.
+@param AndData The value to AND with the PCI configuration register.
+@param OrData The value to OR with the PCI configuration register.
+
+@return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PegPciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+Find the Offset to a Capabilities ID
+@param[in] Segment Pci Segment Number
+@param[in] Bus Pci Bus Number
+@param[in] Device Pci Device Number
+@param[in] Function Pci Function Number
+@param[in] CapId CAPID to search for
+
+@retval 0 CAPID not found
+@retval Other CAPID found, Offset of desired CAPID
+**/
+UINT8
+PegPcieFindCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ );
+#endif // _CPU_PCIE_INIT_COMMON_H_
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h
new file mode 100644
index 0000000000..ebb568193a
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for CpuPcieRpLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIERP_LIB_H_
+#define _CPU_PCIERP_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+#include <Library/HobLib.h>
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Segment;
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ BOOLEAN Enable;
+} CPU_PCIE_RP_INFO;
+
+#pragma pack()
+
+/**
+ Determines whether PCIe link is active
+
+ @param[in] RpBase Root Port base address
+ @retval Link Active state
+**/
+BOOLEAN
+CpuPcieIsLinkActive (
+ UINT64 RpBase
+ );
+
+/**
+ Get max PCIe link speed supported by the root port.
+
+ @param[in] RpBase Root Port pci segment base address
+ @return Max link speed
+**/
+UINT32
+CpuPcieGetMaxLinkSpeed (
+ UINT64 RpBase
+ );
+
+#endif // _CPU_PCIERP_LIB_H_
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Library/DxeCpuPcieRpLib.h
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Library/DxeCpuPcieRpLib.h
new file mode 100644
index 0000000000..593e1893bb
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Library/DxeCpuPcieRpLib.h
@@ -0,0 +1,18 @@
+/** @file
+ Header file for private DxeCpuPcieRpLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_PCIE_RP_INIT_LIB_H_
+#define _DXE_PCIE_RP_INIT_LIB_H_
+
+/**
+ Update CPU PCIE RP NVS AREA tables
+
+**/
+VOID
+UpdateCpuPcieNVS (
+ VOID
+ );
+#endif
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/CpuPcieInitCommon.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/CpuPcieInitCommon.c
new file mode 100644
index 0000000000..28032e5b24
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/CpuPcieInitCommon.c
@@ -0,0 +1,445 @@
+/** @file
+ common library for CPU PCIe INIT PEI/DXE/SMM modules
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/PcieHelperLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/CpuPcieRpLib.h>
+#include <Register/CpuPcieRegs.h>
+#include <Library/CpuPcieInitCommon.h>
+#include <Library/CpuRegbarAccessLib.h>
+
+/**
+ Print registers value
+
+ @param[in] PrintMmioBase Mmio base address
+ @param[in] PrintSize Number of registers
+ @param[in] OffsetFromBase Offset from mmio base address
+
+ @retval None
+**/
+VOID
+SaPrintRegisters (
+ IN UINTN PrintMmioBase,
+ IN UINT32 PrintSize,
+ IN UINT32 OffsetFromBase
+ )
+{
+ UINT32 Offset;
+ DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
0F"));
+ for (Offset = 0; Offset < PrintSize; Offset++) {
+ if ((Offset % 16) == 0) {
+ DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFFF0));
+ }
+ DEBUG ((DEBUG_VERBOSE, "%02X ", MmioRead8 (PrintMmioBase + Offset)));
+ }
+ DEBUG ((DEBUG_VERBOSE, "\n"));
+}
+
+/**
+ Print registers value
+
+ @param[in] PrintPciSegmentBase Pci segment base address
+ @param[in] PrintSize Number of registers
+ @param[in] OffsetFromBase Offset from mmio base address
+
+ @retval None
+**/
+VOID
+SaPrintPciRegisters (
+ IN UINT64 PrintPciSegmentBase,
+ IN UINT32 PrintSize,
+ IN UINT32 OffsetFromBase
+ )
+{
+ UINT32 Offset;
+ DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
0F"));
+ for (Offset = 0; Offset < PrintSize; Offset++) {
+ if ((Offset % 16) == 0) {
+ DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFFF0));
+ }
+ DEBUG ((DEBUG_VERBOSE, "%02X ", PciSegmentRead8 (PrintPciSegmentBase +
Offset)));
+ }
+ DEBUG ((DEBUG_VERBOSE, "\n"));
+}
+
+//
+// 2LM: PegPcie APIs using the Sideband Access Mechanism
+//
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentRead8 function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+**/
+UINT8
+EFIAPI
+PegPciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ return PciSegmentRead8 (Address);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentWrite8
function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PegPciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ return PciSegmentWrite8 (Address, Value);
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentRead16
function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+**/
+UINT16
+EFIAPI
+PegPciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ return PciSegmentRead16 (Address);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentWrite16
function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+**/
+UINT16
+EFIAPI
+PegPciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ return PciSegmentWrite16 (Address, Value);
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentRead32
function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+**/
+UINT32
+EFIAPI
+PegPciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ return PciSegmentRead32 (Address);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentWrite32
function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+**/
+UINT32
+EFIAPI
+PegPciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ return PciSegmentWrite32 (Address, Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit
value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentOr16 function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT16
+EFIAPI
+PegPciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentOr16 (Address, OrData);
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentAnd32 function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PegPciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentAnd16 (Address, AndData);
+}
+
+/**
+ Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bit
value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentAnd8 function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PegPciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentAnd8 (Address, AndData);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit
value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentOr32 function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT32
+EFIAPI
+PegPciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentOr32 (Address, OrData);
+}
+
+/**
+ Performs a bitwise OR of a 8-bit PCI configuration register with a 8-bit
value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentOr8 function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PegPciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentOr8 (Address, OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentAnd32 function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PegPciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentAnd32 (Address, AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
value,
+ followed a bitwise OR with another 32-bit value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentAndThenOr32
function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT32
+EFIAPI
+PegPciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentAndThenOr32 (Address, AndData, OrData);
+}
+
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
value,
+ followed a bitwise OR with another 16-bit value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentAndThenOr16
function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT16
+EFIAPI
+PegPciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentAndThenOr16 (Address, AndData, OrData);
+}
+
+
+/**
+ Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bit
value,
+ followed a bitwise OR with another 8-bit value.
+
+ Its a wrapper library function. This function uses side band access for
PEG60 when 2LM mode is enabled.
+ Other calls to this function will be routed to core PciSegmentAndThenOr8
function.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device,
Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PegPciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentAndThenOr8 (Address, AndData, OrData);
+}
+
+
+/**
+ Find the Offset to a Capabilities ID
+ @param[in] Segment Pci Segment Number
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT8
+PegPcieFindCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ )
+{
+ return PcieFindCapId (Segment, Bus, Device, Function, CapId);
+}
+
+
+/**
+ Search and return the offset of desired Pci Express extended Capability ID
+ @param[in] Segment Pci Segment Number
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId Extended CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT16
+PegPcieFindExtendedCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT16 CapId
+ )
+{
+ return PcieFindExtendedCapId (Segment, Bus, Device, Function, CapId);
+}
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf
new file mode 100644
index 0000000000..2ad30ab7c9
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Component description file for the CpuPcieInitCommonLib
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmCpuPcieInitCommonLib
+ FILE_GUID = 68992CB0-A3A5-4f73-9370-93A3559F84C8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CpuPcieInitCommonLib
+
+[Sources]
+ CpuPcieInitCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ TigerlakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ PciSegmentLib
+ CpuPcieRpLib
+ CpuRegbarAccessLib
+ BasePcieHelperLib
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdCpuPcieEnable ## CONSUMES
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/CpuPcieRpLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/CpuPcieRpLib.c
new file mode 100644
index 0000000000..02cd482b55
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/CpuPcieRpLib.c
@@ -0,0 +1,48 @@
+/** @file
+ CPU PCIe root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <PcieRegs.h>
+#include <Register/CpuPcieRegs.h>
+#include "CpuPcieInfo.h"
+#include <Library/CpuPcieInitCommon.h>
+#include <Library/PciLib.h>
+#include <IndustryStandard/Pci22.h>
+
+/**
+ Determines whether PCIe link is active
+
+ @param[in] RpBase Root Port base address
+ @retval Link Active state
+**/
+BOOLEAN
+CpuPcieIsLinkActive (
+ UINT64 RpBase
+ )
+{
+ return !! (PegPciSegmentRead16 (RpBase + R_PCIE_LSTS) & B_PCIE_LSTS_LA);
+}
+
+/**
+ Get max PCIe link speed supported by the root port.
+
+ @param[in] RpBase Root Port base address
+ @return Max link speed
+**/
+UINT32
+CpuPcieGetMaxLinkSpeed (
+ UINT64 RpBase
+ )
+{
+ return PegPciSegmentRead32 (RpBase + R_PCIE_LCAP) & B_PCIE_LCAP_MLS;
+}
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf
new file mode 100644
index 0000000000..cea8bcbecd
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf
@@ -0,0 +1,32 @@
+## @file
+# CPU PCIE root port Library.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPcieRpLib
+FILE_GUID = 00199A03-41F4-43c7-B6D5-5A3AA1EE78D0
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPcieRpLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PciLib
+
+[Packages]
+MdePkg/MdePkg.dec
+TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+CpuPcieRpLib.c
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c
new file mode 100644
index 0000000000..48ef8165de
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c
@@ -0,0 +1,62 @@
+/** @file
+ The DXE CPU PCIE RP Library Implements After Memory PEIM
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/HobLib.h>
+#include <Library/PciSegmentLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Protocol/SaPolicy.h>
+#include <Protocol/SaNvsArea.h>
+#include <Library/PcdLib.h>
+#include <Library/PciExpressHelpersLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <ConfigBlock/PcieDxeConfig.h>
+#include <Register/SaRegsHostBridge.h>
+
+/**
+Update CPU PCIE RP NVS AREA tables
+
+**/
+VOID
+UpdateCpuPcieNVS (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ PCIE_DXE_CONFIG *PcieDxeConfig;
+ SA_POLICY_PROTOCOL *SaPolicy;
+ SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol;
+
+ DEBUG ((DEBUG_INFO, "Update Cpu Pcie NVS Area.\n"));
+
+ Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **)
&SaPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOID
*)&PcieDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->LocateProtocol (&gSaNvsAreaProtocolGuid, NULL, (VOID **)
&SaNvsAreaProtocol);
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "Locate SA NVS Area failed.\n"));
+ return;
+ }
+
+ SaNvsAreaProtocol->Area->Peg0LtrEnable =
PcieDxeConfig->PegPwrOpt[0].LtrEnable;
+ SaNvsAreaProtocol->Area->Peg0ObffEnable =
PcieDxeConfig->PegPwrOpt[0].ObffEnable;
+ SaNvsAreaProtocol->Area->Peg1LtrEnable =
PcieDxeConfig->PegPwrOpt[1].LtrEnable;
+ SaNvsAreaProtocol->Area->Peg1ObffEnable =
PcieDxeConfig->PegPwrOpt[1].ObffEnable;
+ SaNvsAreaProtocol->Area->Peg2LtrEnable =
PcieDxeConfig->PegPwrOpt[2].LtrEnable;
+ SaNvsAreaProtocol->Area->Peg2ObffEnable =
PcieDxeConfig->PegPwrOpt[2].ObffEnable;
+ SaNvsAreaProtocol->Area->Peg3LtrEnable =
PcieDxeConfig->PegPwrOpt[3].LtrEnable;
+ SaNvsAreaProtocol->Area->Peg3ObffEnable =
PcieDxeConfig->PegPwrOpt[3].ObffEnable;
+ SaNvsAreaProtocol->Area->PegLtrMaxSnoopLatency =
V_SA_LTR_MAX_SNOOP_LATENCY_VALUE;
+ SaNvsAreaProtocol->Area->PegLtrMaxNoSnoopLatency =
V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE;
+}
diff --git
a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf
new file mode 100644
index 0000000000..dc9b893be3
--- /dev/null
+++
b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf
@@ -0,0 +1,40 @@
+## @file
+# The DXE CPU PCIE RP Library Implements After Memory PEIM
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeCpuPcieRpLib
+FILE_GUID = D563A22E-6A01-4EF7-84D1-78B6717E3402
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = DxeCpuPcieRpLib
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+BaseMemoryLib
+UefiBootServicesTableLib
+UefiLib
+HobLib
+
+[Packages]
+MdePkg/MdePkg.dec
+TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+DxeCpuPcieRpLib.c
+
+[Guids]
+gPcieDxeConfigGuid
+
+[Protocols]
+gSaPolicyProtocolGuid ## CONSUMES
+gSaNvsAreaProtocolGuid ## CONSUMES
--
2.24.0.windows.2
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