REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* Include/Pins
* Include/Register
* Include/*.h
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Signed-off-by: Heng Luo <heng....@intel.com>
---
Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h | 53
+++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h | 38
++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h | 75
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h | 138
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h | 57
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h | 24
++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h | 155
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h | 110
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h | 72
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h | 121
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h | 226
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h | 16
++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h | 36
++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h | 93
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h | 258
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h | 45
+++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h | 56
++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h | 47
+++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h | 51
+++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h | 213
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h | 17
+++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h | 64
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
22 files changed, 1965 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 0000000000..ad34e4ea42
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID
extension HOB header
+ UINT8 Revision; ///< Offset 24 Revision
of this config block
+ UINT8 Attributes; ///< Offset 25 The main
revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of
config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID
number for main entry of config block
+ UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved
for future use
+ UINT16 NumberOfBlocks; ///< Offset 30-31 Number of
config blocks (N)
+ UINT32 AvailableSize; ///< Offset 32-35 Current
config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of
AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma pack (pop)
+
+#endif // _CONFIG_BLOCK_H_
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h
new file mode 100644
index 0000000000..23a408e8dc
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h
@@ -0,0 +1,38 @@
+/** @file
+ The GUID definition for CpuPcieHob
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_HOB_H_
+#define _CPU_PCIE_HOB_H_
+
+#include <Base.h>
+#include <CpuPcieInfo.h>
+#include <CpuPcieConfig.h>
+
+extern EFI_GUID gCpuPcieHobGuid;
+#pragma pack (push,1)
+
+/**
+ The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie
controllers
+**/
+typedef struct {
+ ///
+ /// These members describe the configuration of each CPU PCIe root port.
+ ///
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///<
Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< The
L1 Substates configuration of the root port
+
+ UINT32 DekelFwVersionMinor; ///<
Dekel Firmware Minor Version
+ UINT32 DekelFwVersionMajor; ///<
Dekel Firmware Major Version
+ BOOLEAN InitPcieAspmAfterOprom; ///<
1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
+ UINT32 RpEnabledMask; ///<
Rootport enabled mask based on DEVEN register
+ UINT32 RpEnMaskFromDevEn; ///<
Rootport enabled mask based on Device Id
+ UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS];
///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
+ UINT8 SlotSelection; ///<
1=M2 slot, 0=CEMx4 slot
+ BOOLEAN ComplianceTest; ///<
Compliance Test based on policy
+} CPU_PCIE_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h
new file mode 100644
index 0000000000..5b058c7a45
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h
@@ -0,0 +1,75 @@
+/** @file
+ This code defines ACPI DMA Remapping table related definitions.
+ See the System Agent BIOS specification for definition of the table.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DMA_REMAPPING_TABLE_H_
+#define _DMA_REMAPPING_TABLE_H_
+
+#include <Uefi.h>
+#include <Base.h>
+#include <IndustryStandard/DmaRemappingReportingTable.h>
+#include <IndustryStandard/Acpi.h>
+#include <TcssInfo.h>
+
+#pragma pack(1)
+///
+/// DMAR table signature
+///
+#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE 0x52414D44 ///< "DMAR"
+#define EFI_ACPI_DMAR_TABLE_REVISION 2
+#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH 0x10
+#define EFI_ACPI_RMRR_HEADER_LENGTH 0x18
+#define MAX_PCI_DEPTH 5
+
+typedef struct {
+ EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER DeviceScopeStructureHeader;
+ EFI_ACPI_DMAR_PCI_PATH PciPath; // device, function
+} EFI_ACPI_DEV_SCOPE_STRUCTURE;
+
+typedef struct {
+ EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader;
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1];
+} EFI_ACPI_DRHD_ENGINE1_STRUCT;
+
+typedef struct {
+ EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader;
+ //
+ // @todo use PCD
+ //
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2];
+} EFI_ACPI_DRHD_ENGINE3_STRUCT;
+
+typedef struct {
+ EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2];
+} EFI_ACPI_RMRR_USB_STRUC;
+
+typedef struct {
+ EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD
+} EFI_ACPI_RMRR_IGD_STRUC;
+
+typedef struct {
+ EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD - DiSM
+} EFI_ACPI_RMRR_IGD_DISM_STRUC;
+
+typedef struct {
+ EFI_ACPI_DMAR_ANDD_HEADER AnddHeader;
+ UINT8 AcpiObjectName[20];
+} EFI_ACPI_ANDD_STRUC;
+
+typedef struct {
+ EFI_ACPI_DMAR_HEADER DmarHeader;
+ EFI_ACPI_DRHD_ENGINE1_STRUCT DrhdEngine1;
+ EFI_ACPI_DRHD_ENGINE3_STRUCT DrhdEngine3;
+ EFI_ACPI_RMRR_IGD_STRUC RmrrIgd;
+ EFI_ACPI_RMRR_IGD_DISM_STRUC RmrrIgdDism;
+} EFI_ACPI_DMAR_TABLE;
+
+#pragma pack()
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h
new file mode 100644
index 0000000000..edb3855b68
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h
@@ -0,0 +1,138 @@
+/** @file
+ Header file for DxePchHdaNhltLib - NHLT structure definitions.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_HDA_NHLT_H_
+#define _DXE_HDA_NHLT_H_
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// ACPI support protocol instance signature definition.
+//
+#define NHLT_ACPI_TABLE_SIGNATURE SIGNATURE_32 ('N', 'H', 'L', 'T')
+
+// MSFT defined structures
+#define SPEAKER_FRONT_LEFT 0x1
+#define SPEAKER_FRONT_RIGHT 0x2
+#define SPEAKER_FRONT_CENTER 0x4
+#define SPEAKER_BACK_LEFT 0x10
+#define SPEAKER_BACK_RIGHT 0x20
+
+#define KSAUDIO_SPEAKER_MONO (SPEAKER_FRONT_CENTER)
+#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT)
+#define KSAUDIO_SPEAKER_QUAD (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT |
SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)
+
+#define WAVE_FORMAT_EXTENSIBLE 0xFFFE /* Microsoft */
+#define KSDATAFORMAT_SUBTYPE_PCM \
+ {0x00000001, 0x0000, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38,
0x9b, 0x71}}
+
+#pragma pack (push, 1)
+
+typedef struct {
+ UINT16 wFormatTag;
+ UINT16 nChannels;
+ UINT32 nSamplesPerSec;
+ UINT32 nAvgBytesPerSec;
+ UINT16 nBlockAlign;
+ UINT16 wBitsPerSample;
+ UINT16 cbSize;
+} WAVEFORMATEX;
+
+typedef struct {
+ WAVEFORMATEX Format;
+ union {
+ UINT16 wValidBitsPerSample;
+ UINT16 wSamplesPerBlock;
+ UINT16 wReserved;
+ } Samples;
+ UINT32 dwChannelMask;
+ GUID SubFormat;
+} WAVEFORMATEXTENSIBLE;
+
+//
+// List of supported link type.
+//
+enum NHLT_LINK_TYPE
+{
+ HdaNhltLinkHd = 0,
+ HdaNhltLinkDsp = 1,
+ HdaNhltLinkDmic = 2,
+ HdaNhltLinkSsp = 3,
+ HdaNhltLinkInvalid
+};
+
+//
+// List of supported device type.
+//
+enum NHLT_SSP_DEVICE_TYPE
+{
+ HdaNhltSspDeviceBt = 0,
+ HdaNhltSspDeviceI2s = 4,
+ HdaNhltSspDeviceInvalid
+};
+
+enum NHLT_PDM_DEVICE_TYPE
+{
+ HdaNhltPdmDeviceDmic = 0,
+ HdaNhltPdmDeviceInvalid
+};
+
+typedef struct {
+ UINT32 CapabilitiesSize;
+ UINT8 Capabilities[1];
+} SPECIFIC_CONFIG;
+
+typedef struct {
+ WAVEFORMATEXTENSIBLE Format;
+ SPECIFIC_CONFIG FormatConfiguration;
+} FORMAT_CONFIG;
+
+typedef struct {
+ UINT8 FormatsCount;
+ FORMAT_CONFIG FormatsConfiguration[1];
+} FORMATS_CONFIG;
+
+typedef struct {
+ UINT8 DeviceId[16];
+ UINT8 DeviceInstanceId;
+ UINT8 DevicePortId;
+} DEVICE_INFO;
+
+typedef struct {
+ UINT8 DeviceInfoCount;
+ DEVICE_INFO DeviceInformation[1];
+} DEVICES_INFO;
+
+typedef struct {
+ UINT32 EndpointDescriptorLength;
+ UINT8 LinkType;
+ UINT8 InstanceId;
+ UINT16 HwVendorId;
+ UINT16 HwDeviceId;
+ UINT16 HwRevisionId;
+ UINT32 HwSubsystemId;
+ UINT8 DeviceType;
+ UINT8 Direction;
+ UINT8 VirtualBusId;
+ SPECIFIC_CONFIG EndpointConfig;
+ FORMATS_CONFIG FormatsConfig;
+ DEVICES_INFO DevicesInformation;
+} ENDPOINT_DESCRIPTOR;
+
+//
+// High Level Table structure
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'}
+ UINT8 EndpointCount; // Actual number of endpoints
+ ENDPOINT_DESCRIPTOR EndpointDescriptors[1];
+ SPECIFIC_CONFIG OedConfiguration;
+} NHLT_ACPI_TABLE;
+
+#pragma pack (pop)
+
+#endif // _DXE_PCH_HDA_NHLT_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h
new file mode 100644
index 0000000000..ab3f2c9cd0
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h
@@ -0,0 +1,57 @@
+/** @file
+ Header file for HD Audio configuration.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _HDA_H_
+#define _HDA_H_
+
+typedef enum {
+ HdaVc0 = 0,
+ HdaVc1 = 1
+} HDAUDIO_VC_TYPE;
+
+typedef enum {
+ HdaDmicDisabled = 0,
+ HdaDmic2chArray = 1,
+ HdaDmic4chArray = 2,
+ HdaDmic1chArray = 3
+} HDAUDIO_DMIC_TYPE;
+
+typedef enum {
+ HdaLinkFreq6MHz = 0,
+ HdaLinkFreq12MHz = 1,
+ HdaLinkFreq24MHz = 2,
+ HdaLinkFreq48MHz = 3,
+ HdaLinkFreq96MHz = 4,
+ HdaLinkFreqInvalid
+} HDAUDIO_LINK_FREQUENCY;
+
+typedef enum {
+ HdaIDispMode2T = 0,
+ HdaIDispMode1T = 1,
+ HdaIDispMode4T = 2,
+ HdaIDispMode8T = 3,
+ HdaIDispMode16T = 4,
+ HdaIDispTModeInvalid
+} HDAUDIO_IDISP_TMODE;
+
+typedef enum {
+ HdaLink = 0,
+ HdaIDispLink = 1,
+ HdaDmic = 2,
+ HdaSsp = 3,
+ HdaSndw = 4,
+ HdaLinkUnsupported
+} HDAUDIO_LINK_TYPE;
+
+typedef enum {
+ HdaDmicClockSelectBoth = 0,
+ HdaDmicClockSelectClkA = 1,
+ HdaDmicClockSelectClkB = 2,
+ HdaDmicClockSelectInvalid
+} HDAUDIO_DMIC_CLOCK_SELECT;
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h
new file mode 100644
index 0000000000..023ba12daa
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h
@@ -0,0 +1,24 @@
+/** @file
+ Definition for ME common policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _ME_POLICY_COMMON_H_
+#define _ME_POLICY_COMMON_H_
+
+#include <ConfigBlock.h>
+
+#include <MePeiConfig.h>
+
+#ifndef PLATFORM_POR
+#define PLATFORM_POR 0
+#endif
+#ifndef FORCE_ENABLE
+#define FORCE_ENABLE 1
+#endif
+#ifndef FORCE_DISABLE
+#define FORCE_DISABLE 2
+#endif
+
+#endif // _ME_POLICY_COMMON_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h
new file mode 100644
index 0000000000..d98019d1b4
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h
@@ -0,0 +1,155 @@
+/** @file
+ Register names for PCIE standard register
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_REGS_H_
+#define _PCIE_REGS_H_
+
+#include <IndustryStandard/Pci30.h>
+
+//
+// PCI type 0 Header
+//
+#define R_PCI_BCC_OFFSET 0x0B
+
+//
+// PCI type 1 Header
+//
+#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Register
+#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordinate
Bus Number
+#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondary
Bus Number
+
+//
+// PCI Express Capability List Register (CAPID:10h)
+//
+#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express
Capabilities Register (Offset 02h)
+#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4)
///< Device/Port Type
+#define N_PCIE_XCAP_DT 4
+
+#define R_PCIE_DCAP_OFFSET 0x04 ///< Device
Capabilities Register (Offset 04h)
+#define B_PCIE_DCAP_RBER BIT15 ///< Role-Based Error
Reporting
+#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///<
Endpoint L1 Acceptable Latency
+#define N_PCIE_DCAP_E1AL 9
+#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///<
Endpoint L0s Acceptable Latency
+#define N_PCIE_DCAP_E0AL 6
+#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///<
Max_Payload_Size Supported
+
+#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control
Register (Offset 08h)
+#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///<
Max_Payload_Size
+#define N_PCIE_DCTL_MPS 5
+
+#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilities
Register (Offset 0Ch)
+#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power
Management
+#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///<
L1 Exit Latency
+#define N_PCIE_LCAP_EL1 15
+#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///<
L0s Exit Latency
+#define N_PCIE_LCAP_EL0 12
+#define B_PCIE_LCAP_APMS_L0S BIT10
+#define B_PCIE_LCAP_APMS_L1 BIT11
+#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0)
///< Max Link Speed
+#define V_PCIE_LCAP_MLS_GEN3 3
+#define V_PCIE_LCAP_MLS_GEN4 4
+
+#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control
Register (Offset 10h)
+#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock Power
Management
+#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock
Configuration
+#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link
+#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Active
State Power Management (ASPM) Control
+#define V_PCIE_LCTL_ASPM_L0S 1
+#define V_PCIE_LCTL_ASPM_L1 2
+#define V_PCIE_LCTL_ASPM_L0S_L1 3
+
+#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status
Register (Offset 12h)
+#define B_PCIE_LSTS_LA BIT13 ///< Data Link Layer
Link Active
+#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock
Configuration
+#define B_PCIE_LSTS_LT BIT11 ///< Link Training
+#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated Link
Width
+#define N_PCIE_LSTS_NLW 4
+#define B_PCIE_LSTS_CLS 0x000F ///< Current Link
Speed
+
+#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilities
Register (Offset 14h)
+#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug
Capable
+
+#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status
Register (Offset 1Ah)
+#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect
State
+
+#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device
Capabilities 2 Register (Offset 24h)
+#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism
Supported
+
+#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control 2
Register (Offset 28h)
+#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism
Enable
+
+#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0)
///< Target Link Speed
+
+//
+// Latency Tolerance Reporting Extended Capability Registers (CAPID:0018h)
+//
+#define R_PCIE_LTRECH_CID 0x0018
+
+#define R_PCIE_LTRECH_MSLR_OFFSET 0x04
+#define N_PCIE_LTRECH_MSLR_VALUE 0
+#define N_PCIE_LTRECH_MSLR_SCALE 10
+
+#define R_PCIE_LTRECH_MNSLR_OFFSET 0x06
+#define N_PCIE_LTRECH_MNSLR_VALUE 0
+#define N_PCIE_LTRECH_MNSLR_SCALE 10
+
+//
+// Secondary PCI Express Extended Capability Header (CAPID:0019h)
+//
+#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3
Register
+#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform
Equalization
+
+//
+// L1 Sub-States Extended Capability Register (CAPID:001Eh)
+//
+#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID
+#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States
Capabilities
+#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpower_on
value
+#define N_PCIE_EX_L1SCAP_PTV 19
+#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port Tpower_on
scale
+#define N_PCIE_EX_L1SCAP_PTPOS 16
+#define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common Mode
Restore time
+#define N_PCIE_EX_L1SCAP_CMRT 8
+#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates
supported
+#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 supported
+#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported
+#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1
supported
+#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2
supported
+#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States
Control 1
+#define B_PCIE_EX_L1SCTL1_L1SSEIE BIT4
+#define N_PCIE_EX_L1SCTL1_L12LTRTLSV 29
+#define N_PCIE_EX_L1SCTL1_L12LTRTLV 16
+#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States
Control 2
+#define N_PCIE_EX_L1SCTL2_POWT 3
+
+//
+// PTM Extended Capability Register (CAPID:001Fh)
+//
+#define V_PCIE_EX_PTM_CID 0x001F ///< Capability ID
+#define R_PCIE_EX_PTMCAP_OFFSET 0x04 ///< PTM Capabilities
+#define R_PCIE_EX_PTMCTL_OFFSET 0x08 ///< PTM Control
Register
+
+//
+// Base Address Offset
+//
+#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2)
+#define B_PCI_BAR_MEMORY_TYPE_64 BIT2
+
+//
+// PCI Express Extended Capability Header
+//
+#define R_PCIE_CFG_EXCAP_OFFSET 0x100
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
new file mode 100644
index 0000000000..ef94790985
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
@@ -0,0 +1,110 @@
+/** @file
+ GPIO pins for TGL-PCH-LP,
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PINS_VER2_LP_H_
+#define _GPIO_PINS_VER2_LP_H_
+///
+/// This header file should be used together with
+/// PCH GPIO lib in C and ASL. All defines used
+/// must match both ASL/C syntax
+///
+
+///
+/// Unique ID used in GpioPad defines
+///
+#define GPIO_VER2_LP_CHIPSET_ID 0x9
+
+///
+/// TGL LP GPIO Groups
+/// Use below for functions from PCH GPIO Lib which
+/// require GpioGroup as argument
+///
+#define GPIO_VER2_LP_GROUP_GPP_B 0x0900
+#define GPIO_VER2_LP_GROUP_GPP_A 0x0902
+#define GPIO_VER2_LP_GROUP_GPP_R 0x0903
+#define GPIO_VER2_LP_GROUP_GPD 0x0905
+#define GPIO_VER2_LP_GROUP_GPP_S 0x0906
+#define GPIO_VER2_LP_GROUP_GPP_H 0x0907
+#define GPIO_VER2_LP_GROUP_GPP_D 0x0908
+#define GPIO_VER2_LP_GROUP_GPP_C 0x090B
+#define GPIO_VER2_LP_GROUP_GPP_F 0x090C
+#define GPIO_VER2_LP_GROUP_GPP_E 0x090E
+
+
+///
+/// TGL LP GPIO pins
+/// Use below for functions from PCH GPIO Lib which
+/// require GpioPad as argument. Encoding used here
+/// has all information required by library functions
+///
+#define GPIO_VER2_LP_GPP_B2 0x09000002
+#define GPIO_VER2_LP_GPP_B4 0x09000004
+#define GPIO_VER2_LP_GPP_B14 0x0900000E
+#define GPIO_VER2_LP_GPP_B15 0x0900000F
+#define GPIO_VER2_LP_GPP_B16 0x09000010
+#define GPIO_VER2_LP_GPP_B18 0x09000012
+#define GPIO_VER2_LP_GPP_B23 0x09000017
+#define GPIO_VER2_LP_GSPI0_CLK_LOOPBK 0x09000018
+
+#define GPIO_VER2_LP_GPP_A10 0x0902000A
+#define GPIO_VER2_LP_GPP_A11 0x0902000B
+#define GPIO_VER2_LP_GPP_A13 0x0902000D
+#define GPIO_VER2_LP_GPP_A14 0x0902000E
+#define GPIO_VER2_LP_GPP_A23 0x09020017
+#define GPIO_VER2_LP_ESPI_CLK_LOOPBK 0x09020018
+
+#define GPIO_VER2_LP_GPP_R5 0x09030005
+#define GPIO_VER2_LP_GPP_R6 0x09030006
+
+#define GPIO_VER2_LP_GPD7 0x09050007
+
+#define GPIO_VER2_LP_INPUT3VSEL 0x0905000C
+
+#define GPIO_VER2_LP_GPP_H0 0x09070000
+#define GPIO_VER2_LP_GPP_H1 0x09070001
+#define GPIO_VER2_LP_GPP_H12 0x0907000C
+#define GPIO_VER2_LP_GPP_H13 0x0907000D
+#define GPIO_VER2_LP_GPP_H15 0x0907000F
+#define GPIO_VER2_LP_GPP_H19 0x09070013
+
+#define GPIO_VER2_LP_GPP_D16 0x09080010
+#define GPIO_VER2_LP_GSPI2_CLK_LOOPBK 0x09080014
+
+#define GPIO_VER2_LP_GPP_C2 0x090B0002
+#define GPIO_VER2_LP_GPP_C5 0x090B0005
+#define GPIO_VER2_LP_GPP_C8 0x090B0008
+#define GPIO_VER2_LP_GPP_C12 0x090B000C
+#define GPIO_VER2_LP_GPP_C13 0x090B000D
+#define GPIO_VER2_LP_GPP_C14 0x090B000E
+#define GPIO_VER2_LP_GPP_C15 0x090B000F
+#define GPIO_VER2_LP_GPP_C22 0x090B0016
+#define GPIO_VER2_LP_GPP_C23 0x090B0017
+
+#define GPIO_VER2_LP_GPP_F4 0x090C0004
+#define GPIO_VER2_LP_GPP_F5 0x090C0005
+#define GPIO_VER2_LP_GPP_F9 0x090C0009
+#define GPIO_VER2_LP_GPP_F10 0x090C000A
+#define GPIO_VER2_LP_GPP_F20 0x090C0014
+#define GPIO_VER2_LP_GPP_F21 0x090C0015
+#define GPIO_VER2_LP_GPPF_CLK_LOOPBK 0x090C0018
+
+#define GPIO_VER2_LP_GPP_E3 0x090E0003
+#define GPIO_VER2_LP_GPP_E7 0x090E0007
+#define GPIO_VER2_LP_GPP_E8 0x090E0008
+#define GPIO_VER2_LP_GPP_E22 0x090E0016
+#define GPIO_VER2_LP_GPP_E23 0x090E0017
+#define GPIO_VER2_LP_GPPE_CLK_LOOPBK 0x090E0018
+
+//
+// GPIO Pin Muxing
+// Determines a selection of physical pad for a given signal.
+// Please refer to GPIO_NATIVE_PAD type.
+// If certain signal is not listed below it means that it can be enabled
+// only on a single pad and muxing setting is not needed.
+//
+#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_H8 0x1947CC08
+#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_H9 0x1947AC09
+#endif // _GPIO_PINS_VER2_LP_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h
new file mode 100644
index 0000000000..215fd0407e
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h
@@ -0,0 +1,72 @@
+/** @file
+ Register names for Flash registers
+
+ Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_REGS_H_
+#define _FLASH_REGS_H_
+
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_FLASH_FDBAR_FLASH_MAP0 0x04
+#define B_FLASH_FDBAR_NC 0x00000300 ///<
Number Of Components
+#define N_FLASH_FDBAR_NC 8 ///<
Number Of Components
+#define R_FLASH_FDBAR_FLASH_MAP1 0x08
+#define B_FLASH_FDBAR_FPSBA 0x00FF0000 ///<
PCH Strap Base Address, [23:16] represents [11:4]
+#define N_FLASH_FDBAR_FPSBA 16 ///<
PCH Strap base Address bit position
+#define N_FLASH_FDBAR_FPSBA_REPR 4 ///<
PCH Strap base Address bit represents position
+#define B_FLASH_FDBAR_PCHSL 0xFF000000 ///<
PCH Strap Length, [31:24] represents number of Dwords
+#define N_FLASH_FDBAR_PCHSL 24 ///<
PCH Strap Length bit position
+#define R_FLASH_FDBAR_FLASH_MAP2 0x0C
+#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC ///<
CPU Strap Base Address [11:2]
+#define N_FLASH_FDBAR_FCPUSBA 2 ///<
CPU Strap Base Address bit position
+#define B_FLASH_FDBAR_CPUSL 0x00FF0000 ///<
CPU Strap Length, [23:16] represents number of Dwords
+#define N_FLASH_FDBAR_CPUSL 16 ///<
CPU Strap Length bit position
+
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_FLASH_FCBA_FLCOMP 0x00 ///<
Flash Components Register
+#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 ///<
Flash Component 1 Size MASK
+#define N_FLASH_FLCOMP_COMP1 4 ///<
Flash Component 1 Size bit position
+#define B_FLASH_FLCOMP_COMP0_MASK 0x0F ///<
Flash Component 0 Size MASK
+#define V_FLASH_FLCOMP_COMP_512KB 0x80000
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_FLASH_UMAP1 0xEFC ///<
Flash Upper Map 1
+#define B_FLASH_UMAP1_MDTBA 0xFF000000 ///<
MIP Descriptor Table Base Address
+#define N_FLASH_UMAP1_MDTBA 24 ///<
MDTBA bits position
+#define N_FLASH_UMAP1_MDTBA_REPR 4 ///<
MDTBA address representation position
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h
new file mode 100644
index 0000000000..e4bf2018b7
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h
@@ -0,0 +1,121 @@
+/** @file
+ Register names for PCH GPIO
+
+Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_H_
+#define _GPIO_REGS_H_
+
+//
+// PADCFG register is split into multiple DW registers
+// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers for
one pad
+//
+#define S_GPIO_PCR_PADCFG 0x10
+
+//
+// Pad Configuration Register DW0
+//
+
+//Pad Reset Config
+#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30)
+#define N_GPIO_PCR_RST_CONF 30
+#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00
+#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01
+#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02
+#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group
+
+//RX Raw Override to 1
+#define B_GPIO_PCR_RX_RAW1 BIT28
+#define N_GPIO_PCR_RX_RAW1 28
+
+//RX Level/Edge Configuration
+#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
+#define N_GPIO_PCR_RX_LVL_EDG 25
+
+//RX Invert
+#define B_GPIO_PCR_RXINV BIT23
+#define N_GPIO_PCR_RXINV 23
+
+//GPIO Input Route IOxAPIC
+#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
+
+//GPIO Input Route SCI
+#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
+
+//GPIO Input Route SMI
+#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
+
+//GPIO Input Route NMI
+#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
+#define N_GPIO_PCR_RX_NMI_ROUTE 17
+
+//GPIO Pad Mode
+#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_PAD_MODE 10
+
+//GPIO RX Disable
+#define B_GPIO_PCR_RXDIS BIT9
+
+//GPIO TX Disable
+#define B_GPIO_PCR_TXDIS BIT8
+#define N_GPIO_PCR_TXDIS 8
+
+//GPIO RX State
+#define B_GPIO_PCR_RX_STATE BIT1
+#define N_GPIO_PCR_RX_STATE 1
+
+//GPIO TX State
+#define B_GPIO_PCR_TX_STATE BIT0
+#define N_GPIO_PCR_TX_STATE 0
+
+//Termination
+#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_TERM 10
+
+//Interrupt number
+#define B_GPIO_PCR_INTSEL 0x7F
+#define N_GPIO_PCR_INTSEL 0
+
+///
+/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
+/// Below defines are to be used internally by PCH SMI dispatcher only
+///
+#define PCH_GPIO_NUM_SUPPORTED_GPIS 512
+#define S_GPIO_PCR_GP_SMI_STS 4
+
+///
+/// Groups mapped to 2-tier General Purpose Event will all be under
+/// one master GPE_111 (0x6F)
+///
+#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F
+
+#endif // _GPIO_REGS_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h
new file mode 100644
index 0000000000..1dc05869dd
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h
@@ -0,0 +1,226 @@
+/** @file
+ Register names for VER2 GPIO
+
+Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_VER2_H_
+#define _GPIO_REGS_VER2_H_
+
+//
+// PCH-LP GPIO
+//
+#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26
+#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17
+#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21
+#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_CPU_PAD_MAX 15
+
+//
+// PCH-LP GPIO registers
+//
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x9A0
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x900
+
+//
+// GPIO Community 2 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700
+
+//
+// GPIO Community 4 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x880
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0xA70
+
+//
+// GPIO Community 5 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x700
+
+#endif // _GPIO_REGS_VER2_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h
new file mode 100644
index 0000000000..5447fabccf
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h
@@ -0,0 +1,16 @@
+/** @file
+ Register names for PCH DMI SIP14
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI14_REGS_H_
+#define _PCH_DMI14_REGS_H_
+
+//
+// DMI Control
+//
+#define R_PCH_DMI14_PCR_DMIC 0x2234
///< DMI Control
+#define B_PCH_DMI14_PCR_DMIC_SRL BIT31
///< Secured register lock
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h
new file mode 100644
index 0000000000..e9e6f80327
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h
@@ -0,0 +1,36 @@
+/** @file
+ Register names for PCH DMI and OP-DMI
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_REGS_H_
+#define _PCH_DMI_REGS_H_
+
+//
+// PCH DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// PCH DMI Source Decode PCRs (Common)
+//
+#define R_PCH_DMI_PCR_LPCLGIR1 0x2730
///< LPC Generic I/O Range 1
+#define R_PCH_DMI_PCR_LPCGMR 0x2740
///< LPC Generic Memory Range
+#define R_PCH_DMI_PCR_SEGIR 0x27BC
///< Second ESPI Generic I/O Range
+#define R_PCH_DMI_PCR_SEGMR 0x27C0
///< Second ESPI Generic Memory Range
+#define R_PCH_DMI_PCR_LPCBDE 0x2744
///< LPC BIOS Decode Enable
+#define R_PCH_DMI_PCR_UCPR 0x2748
///< uCode Patch Region
+#define B_PCH_DMI_PCR_UCPR_UPRE BIT0
///< uCode Patch Region Enable
+#define R_PCH_DMI_PCR_GCS 0x274C
///< Generic Control and Status
+#define B_PCH_DMI_PCR_BBS BIT10
///< Boot BIOS Strap
+#define B_PCH_DMI_PCR_RPR BIT11
///< Reserved Page Route
+#define B_PCH_DMI_PCR_BILD BIT0
///< BIOS Interface Lock-Down
+#define R_PCH_DMI_PCR_IOT1 0x2750
///< I/O Trap Register 1
+#define R_PCH_DMI_PCR_LPCIOD 0x2770
///< LPC I/O Decode Ranges
+#define R_PCH_DMI_PCR_LPCIOE 0x2774
///< LPC I/O Enables
+#define R_PCH_DMI_PCR_TCOBASE 0x2778
///< TCO Base Address
+#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0
///< TCO Base Address Mask
+#define R_PCH_DMI_PCR_GPMR1 0x277C
///< General Purpose Memory Range 1
+#define R_PCH_DMI_PCR_GPMR1DID 0x2780
///< General Purpose Memory Range 1 Destination ID
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
new file mode 100644
index 0000000000..c3497b1013
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
@@ -0,0 +1,93 @@
+/** @file
+ Register names for PCH PCI-E root port devices
+
+ Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+#define R_PCH_PCIE_CFG_CLIST 0x40
+#define R_PCH_PCIE_CFG_LCAP (R_PCH_PCIE_CFG_CLIST +
R_PCIE_LCAP_OFFSET)
+#define N_PCH_PCIE_CFG_LCAP_PN 24
+#define R_PCH_PCIE_CFG_LCTL (R_PCH_PCIE_CFG_CLIST +
R_PCIE_LCTL_OFFSET)
+#define R_PCH_PCIE_CFG_LSTS (R_PCH_PCIE_CFG_CLIST +
R_PCIE_LSTS_OFFSET)
+#define R_PCH_PCIE_CFG_SLCAP (R_PCH_PCIE_CFG_CLIST +
R_PCIE_SLCAP_OFFSET)
+#define R_PCH_PCIE_CFG_SLSTS (R_PCH_PCIE_CFG_CLIST +
R_PCIE_SLSTS_OFFSET)
+
+#define R_PCH_PCIE_CFG_MPC2 0xD4
+#define B_PCH_PCIE_CFG_MPC2_EOIFD BIT1
+
+#define R_PCH_PCIE_CFG_MPC 0xD8
+#define S_PCH_PCIE_CFG_MPC 4
+#define B_PCH_PCIE_CFG_MPC_PMCE BIT31
+#define B_PCH_PCIE_CFG_MPC_HPME BIT1
+#define N_PCH_PCIE_CFG_MPC_HPME 1
+
+#define R_PCH_PCIE_CFG_SMSCS 0xDC
+#define S_PCH_PCIE_CFG_SMSCS 4
+#define B_PCH_PCIE_CFG_SMSCS_PMCS BIT31
+#define N_PCH_PCIE_CFG_SMSCS_LERSMIS 5
+#define N_PCH_PCIE_CFG_SMSCS_HPLAS 4
+#define N_PCH_PCIE_CFG_SMSCS_HPPDM 1
+
+//CES.RE, CES.BT, CES.BD
+
+#define R_PCH_PCIE_CFG_EX_SPEECH 0xA30 ///< Secondary PCI
Express Extended Capability Header
+#define R_PCH_PCIE_CFG_EX_LCTL3
(R_PCH_PCIE_CFG_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET)
+
+#define R_PCH_PCIE_CFG_LTROVR 0x400
+#define B_PCH_PCIE_CFG_LTROVR_LTRNSROVR BIT31 ///< LTR Non-Snoop
Requirement Bit Override
+#define B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15 ///< LTR Snoop
Requirement Bit Override
+
+#define R_PCH_PCIE_CFG_LTROVR2 0x404
+#define B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE BIT3 ///< LTR Force
Override Enable
+#define B_PCH_PCIE_CFG_LTROVR2_LOCK BIT2 ///< LTR Override
Lock
+#define B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN BIT1 ///< LTR Non-Snoop
Override Enable
+#define B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN BIT0 ///< LTR Snoop
Override Enable
+
+#define R_PCH_PCIE_CFG_PCIEPMECTL 0x420
+#define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE BIT30
+#define B_PCH_PCIE_CFG_PCIEPMECTL_L1LE BIT17
+#define B_PCH_PCIE_CFG_PCIEPMECTL_L1FSOE BIT0
+
+#define R_PCH_PCIE_CFG_EQCFG1 0x450
+#define S_PCH_PCIE_CFG_EQCFG1 4
+#define N_PCH_PCIE_CFG_EQCFG1_LERSMIE 21
+
+//
+// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
+//
+#define R_SPX_PCR_PCD 0 ///<
Port configuration and disable
+#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///<
Port 1 Function Number
+#define S_SPX_PCR_PCD_RP_FIELD 4 ///< 4
bits for each RP FN
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h
new file mode 100644
index 0000000000..fac1497773
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h
@@ -0,0 +1,258 @@
+/** @file
+ Register names for PCH PMC device
+
+ Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PMC_H_
+#define _PCH_REGS_PMC_H_
+
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_ACPI_IO_PM1_STS 0x00
+#define S_ACPI_IO_PM1_STS 2
+#define B_ACPI_IO_PM1_STS_WAK BIT15
+#define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14
+#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
+#define B_ACPI_IO_PM1_STS_RTC BIT10
+#define B_ACPI_IO_PM1_STS_PWRBTN BIT8
+#define B_ACPI_IO_PM1_STS_GBL BIT5
+#define B_ACPI_IO_PM1_STS_TMROF BIT0
+#define N_ACPI_IO_PM1_STS_RTC 10
+#define N_ACPI_IO_PM1_STS_PWRBTN 8
+#define N_ACPI_IO_PM1_STS_TMROF 0
+
+#define R_ACPI_IO_PM1_EN 0x02
+#define S_ACPI_IO_PM1_EN 2
+#define B_ACPI_IO_PM1_EN_PWRBTN BIT8
+#define N_ACPI_IO_PM1_EN_RTC 10
+#define N_ACPI_IO_PM1_EN_PWRBTN 8
+#define N_ACPI_IO_PM1_EN_TMROF 0
+
+#define R_ACPI_IO_PM1_CNT 0x04
+#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13
+#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
+#define V_ACPI_IO_PM1_CNT_S0 0
+#define V_ACPI_IO_PM1_CNT_S1 BIT10
+#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
+#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
+#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
+#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0
+
+#define R_ACPI_IO_PM1_TMR 0x08
+#define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF
+#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The
timer is 24 bit overflow
+
+#define R_ACPI_IO_SMI_EN 0x30
+#define S_ACPI_IO_SMI_EN 4
+#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
+#define B_ACPI_IO_SMI_EN_TCO BIT13
+#define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7
+#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
+#define B_ACPI_IO_SMI_EN_APMC BIT5
+#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
+#define B_ACPI_IO_SMI_EN_BIOS BIT2
+#define B_ACPI_IO_SMI_EN_EOS BIT1
+#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
+#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_EN_ESPI 28
+#define N_ACPI_IO_SMI_EN_PERIODIC 14
+#define N_ACPI_IO_SMI_EN_TCO 13
+#define N_ACPI_IO_SMI_EN_MCSMI 11
+#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_EN_APMC 5
+#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_EN_LEGACY_USB 3
+
+#define R_ACPI_IO_SMI_STS 0x34
+#define S_ACPI_IO_SMI_STS 4
+#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
+#define B_ACPI_IO_SMI_STS_SMBUS BIT16
+#define B_ACPI_IO_SMI_STS_PERIODIC BIT14
+#define B_ACPI_IO_SMI_STS_TCO BIT13
+#define B_ACPI_IO_SMI_STS_MCSMI BIT11
+#define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6
+#define B_ACPI_IO_SMI_STS_APM BIT5
+#define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4
+#define B_ACPI_IO_SMI_STS_BIOS BIT2
+#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_STS_ESPI 28
+#define N_ACPI_IO_SMI_STS_SPI 26
+#define N_ACPI_IO_SMI_STS_MONITOR 21
+#define N_ACPI_IO_SMI_STS_PCI_EXP 20
+#define N_ACPI_IO_SMI_STS_SMBUS 16
+#define N_ACPI_IO_SMI_STS_SERIRQ 15
+#define N_ACPI_IO_SMI_STS_PERIODIC 14
+#define N_ACPI_IO_SMI_STS_TCO 13
+#define N_ACPI_IO_SMI_STS_MCSMI 11
+#define N_ACPI_IO_SMI_STS_GPIO_SMI 10
+#define N_ACPI_IO_SMI_STS_GPE0 9
+#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
+#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_STS_APM 5
+#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_STS_LEGACY_USB 3
+
+#define R_ACPI_IO_DEVACT_STS 0x44
+#define B_ACPI_IO_DEVACT_STS_KBC BIT12
+#define B_ACPI_IO_DEVACT_STS_PIRQDH BIT9
+#define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8
+#define B_ACPI_IO_DEVACT_STS_PIRQBF BIT7
+#define B_ACPI_IO_DEVACT_STS_PIRQAE BIT6
+
+#define R_ACPI_IO_GPE0_STS_127_96 0x6C
+#define S_ACPI_IO_GPE0_STS_127_96 4
+#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
+#define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17
+#define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16
+#define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13
+#define B_ACPI_IO_GPE0_STS_127_96_PME BIT11
+#define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10
+#define B_ACPI_IO_GPE0_STS_127_96_RI BIT8
+#define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7
+#define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2
+#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_STS_127_96_PME 11
+
+#define R_ACPI_IO_GPE0_EN_127_96 0x7C
+#define S_ACPI_IO_GPE0_EN_127_96 4
+#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
+#define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16
+#define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13
+#define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12
+#define B_ACPI_IO_GPE0_EN_127_96_PME BIT11
+#define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10
+#define B_ACPI_IO_GPE0_EN_127_96_RI BIT8
+#define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2
+#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_EN_127_96_PME 11
+
+//
+// TCO register I/O map
+//
+#define R_TCO_IO_TCO1_STS 0x04
+#define S_TCO_IO_TCO1_STS 2
+#define B_TCO_IO_TCO1_STS_DMISERR BIT12
+#define B_TCO_IO_TCO1_STS_DMISMI BIT10
+#define B_TCO_IO_TCO1_STS_DMISCI BIT9
+#define B_TCO_IO_TCO1_STS_BIOSWR BIT8
+#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
+#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
+#define B_TCO_IO_TCO1_STS_TCO_INT BIT2
+#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
+#define N_TCO_IO_TCO1_STS_DMISMI 10
+#define N_TCO_IO_TCO1_STS_BIOSWR 8
+#define N_TCO_IO_TCO1_STS_NEWCENTURY 7
+#define N_TCO_IO_TCO1_STS_TIMEOUT 3
+#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
+#define N_TCO_IO_TCO1_STS_NMI2SMI 0
+
+#define R_TCO_IO_TCO2_STS 0x06
+#define S_TCO_IO_TCO2_STS 2
+#define B_TCO_IO_TCO2_STS_SECOND_TO BIT1
+#define B_TCO_IO_TCO2_STS_INTRD_DET BIT0
+#define N_TCO_IO_TCO2_STS_INTRD_DET 0
+
+#define R_TCO_IO_TCO1_CNT 0x08
+#define S_TCO_IO_TCO1_CNT 2
+#define B_TCO_IO_TCO1_CNT_LOCK BIT12
+#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9
+
+#define R_TCO_IO_TCO2_CNT 0x0A
+#define S_TCO_IO_TCO2_CNT 2
+#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
+
+//
+// PWRM Registers
+//
+#define R_PMC_PWRM_GEN_PMCON_A 0x1020
///< in CNL located in PWRM
+#define B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24
+#define B_PMC_PWRM_GEN_PMCON_A_DISB BIT23
+#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19
+#define B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18
+#define B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16
+#define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14
+#define B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9
+#define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8
+#define B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN BIT0
+#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00
+#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL 0x6
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006
+
+#define R_PMC_PWRM_GEN_PMCON_B 0x1024
+#define B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18
///< Lock down SLP_S3/SLP_S4 Minimum Assertion width
+#define B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9
+#define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4
+#define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2
+
+#define R_PMC_PWRM_CRID 0x1030
///< Configured Revision ID
+#define V_PMC_PWRM_CRID_RID_SEL_CRID0 1
+#define B_PMC_PWRM_CRID_CRID_LK BIT31
///< CRID Lock
+
+#define R_PMC_PWRM_ETR3 0x1048
///< in CNL this is PWRM register
+#define B_PMC_PWRM_ETR3_CF9LOCK BIT31
///< CF9h Lockdown
+#define B_PMC_PWRM_ETR3_CF9GR BIT20
///< CF9h Global Reset
+#define B_PMC_PWRM_ETR3_CWORWRE BIT18
+
+#define R_PMC_PWRM_CFG 0x1818
///< Power Management Configuration
+#define B_PMC_PWRM_CFG_DBG_MODE_LOCK BIT27
///< Debug Mode Lock
+#define B_PMC_PWRM_CFG_PMCREAD_DISABLE BIT22
///< Disable Reads to PMC
+#define B_PMC_PWRM_CFG_TIMING_TPCH25 (BIT1 | BIT0)
///< tPCH25 timing
+
+#define R_PMC_PWRM_DSX_CFG 0x1834
///< Deep SX Configuration
+#define B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0
///< LAN_WAKE Pin DeepSx Enable
+
+#define R_PMC_PWRM_GPIO_CFG 0x1920
+#define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 |
BIT9 | BIT8)
+#define N_PMC_PWRM_GPIO_CFG_GPE0_DW2 8
+#define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 |
BIT5 | BIT4)
+#define N_PMC_PWRM_GPIO_CFG_GPE0_DW1 4
+#define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 |
BIT1 | BIT0)
+#define N_PMC_PWRM_GPIO_CFG_GPE0_DW0 0
+
+#define R_PMC_PWRM_HPR_CAUSE0 0x192C ///< Host
partition reset causes
+#define B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///<
Global reset converted to Host reset
+
+#define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20 ///< Static
PG Related Function Disable Register 1
+#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static
Function Disable Lock (ST_FDIS_LK)
+
+#define R_PMC_PWRM_FUSE_DIS_RD_2 0x1E44 ///< Fuse
Disable Read 2 Register
+#define B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE
Fuse or Soft Strap Disable
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h
new file mode 100644
index 0000000000..5824663d22
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h
@@ -0,0 +1,45 @@
+/** @file
+ Register names for RTC device
+
+Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _REGS_RTC_H_
+#define _REGS_RTC_H_
+
+#define R_RTC_IO_INDEX 0x70
+#define R_RTC_IO_TARGET 0x71
+#define R_RTC_IO_INDEX_ALT 0x74
+#define R_RTC_IO_TARGET_ALT 0x75
+#define R_RTC_IO_EXT_INDEX_ALT 0x76
+#define R_RTC_IO_REGD 0x0D
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h
new file mode 100644
index 0000000000..2037bb003d
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h
@@ -0,0 +1,56 @@
+/** @file
+ Register names for SATA controllers
+
+ Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SATA_REGS_H_
+#define _SATA_REGS_H_
+
+//
+// SATA Controller Common Registers
+//
+#define R_SATA_CFG_AHCI_BAR 0x24
+#define R_SATA_CFG_MAP 0x90
+#define N_SATA_CFG_MAP_SPD 16
+#define R_SATA_CFG_PCS 0x94
+#define B_SATA_CFG_PCS_P0P BIT16
+#define R_SATA_CFG_SATAGC 0x9C
+#define B_SATA_CFG_SATAGC_ASSEL (BIT2 | BIT1 | BIT0)
+#define V_SATA_CFG_SATAGC_ASSEL_2K 0x0
+#define V_SATA_CFG_SATAGC_ASSEL_16K 0x1
+#define V_SATA_CFG_SATAGC_ASSEL_32K 0x2
+#define V_SATA_CFG_SATAGC_ASSEL_64K 0x3
+#define V_SATA_CFG_SATAGC_ASSEL_128K 0x4
+#define V_SATA_CFG_SATAGC_ASSEL_256K 0x5
+#define V_SATA_CFG_SATAGC_ASSEL_512K 0x6
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h
new file mode 100644
index 0000000000..9864dd872d
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h
@@ -0,0 +1,47 @@
+/** @file
+ Register names for Serial IO Controllers
+
+ Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_REGS_H_
+#define _SERIAL_IO_REGS_H_
+
+//
+// Serial IO Controllers PCI Configuration Registers
+// registers accessed using PciD21FxRegBase + offset
+//
+#define R_SERIAL_IO_CFG_BAR0_LOW 0x10
+#define R_SERIAL_IO_CFG_BAR0_HIGH 0x14
+
+#define R_SERIAL_IO_CFG_PME_CTRL_STS 0x84
+
+#endif //_SERIAL_IO_REGS_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h
new file mode 100644
index 0000000000..ea832873bf
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h
@@ -0,0 +1,51 @@
+/** @file
+ Register names for USB Host and device controller
+
+ Conventions:
+
+ - Register definition format:
+
Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g.
PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register
belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _USB_REGS_H_
+#define _USB_REGS_H_
+
+//
+// XHCI PCI Config Space registers
+//
+#define R_XHCI_CFG_PWR_CNTL_STS 0x74
+#define B_XHCI_CFG_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
+#define V_XHCI_CFG_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
+
+//
+// xDCI (OTG) MMIO registers
+//
+#define R_XDCI_MEM_GCTL 0xC110 ///< Xdci Global Ctrl
+
+#endif // _USB_REGS_H_
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h
new file mode 100644
index 0000000000..e2e1cf2ad2
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h
@@ -0,0 +1,213 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_DEVICES_H_
+#define _SERIAL_IO_DEVICES_H_
+
+#include <Protocol/SerialIo.h>
+#include <PchLimits.h>
+
+#pragma pack (push,1)
+
+/**
+ Available working modes for SerialIo SPI Host Controller
+
+ 0: SerialIoSpiDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions
on given device
+ are enabled, PSF disabling is skipped. PSF default will
remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions
above 0 in a multifunction device.
+ <b>1: SerialIoSpiPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoSpiHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported
as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to
hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoSpiDisabled,
+ SerialIoSpiPci,
+ SerialIoSpiHidden
+} SERIAL_IO_SPI_MODE;
+
+/**
+ Used to set Inactive/Idle polarity of Spi Chip Select
+**/
+typedef enum {
+ SerialIoSpiCsActiveLow = 0,
+ SerialIoSpiCsActiveHigh = 1
+} SERIAL_IO_CS_POLARITY;
+
+/**
+ The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO
SPI controller
+**/
+typedef struct {
+ UINT8 Mode; ///< <b>SerialIoSpiPci
</b> see SERIAL_IO_SPI_MODE
+ UINT8 DefaultCsOutput; ///< <b>0 = CS0</b>
CS1, CS2, CS3. Default CS used by the SPI HC
+ UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI
ChipSelect signal polarity, 0 = low <b>1 = High</b>
+ UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b>
1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured
in Native mode
+ UINT8 CsMode; ///< <b>0 = HW
Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
+ UINT8 CsState; ///< <b>0 = CS is set
to low</b> 1 = CS is set to high
+} SERIAL_IO_SPI_CONFIG;
+
+/**
+ Available working modes for SerialIo UART Host Controller
+
+ 0: SerialIoUartDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions
on given device
+ are enabled, PSF disabling is skipped. PSF default will
remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions
above 0 in a multifunction device.
+ <b>1: SerialIoUartPci;</b>
+ - Designated for Serial IO UART OS driver usage
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoUartHidden;
+ - Designated for BIOS and/or DBG2 OS kernel debug
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported
as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to
hidden it will not be visible in the PCI space.
+ 3: SerialIoUartCom;
+ - Designated for 16550/PNP0501 compatible COM device
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported
as motherboard resource by SIRC
+ 4: SerialIoUartSkipInit;
+ - Gpio configuration is skipped
+ - PSF configuration is skipped
+ - BAR assignemnt is skipped
+ - D-satate setting is skipped
+
+**/
+typedef enum {
+ SerialIoUartDisabled,
+ SerialIoUartPci,
+ SerialIoUartHidden,
+ SerialIoUartCom,
+ SerialIoUartSkipInit
+} SERIAL_IO_UART_MODE;
+
+/**
+ UART Settings
+**/
+typedef struct {
+ UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec
PcdUartDefaultBaudRate
+ UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE
MdePkg.dec PcdUartDefaultParity
+ UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
+ UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE
MdePkg.dec PcdUartDefaultStopBits
+ UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc
PcdIsaBusSerialUseHalfHandshake
+} SERIAL_IO_UART_ATTRIBUTES;
+
+/**
+ UART signals pin muxing settings. If signal can be enable only on a single
pin
+ then this parameter is ignored by RC. Refer to
GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Rx; ///< RXD Pin mux configuration. Refer to
GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
+ UINT32 Tx; ///< TXD Pin mux configuration. Refer to
GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
+ UINT32 Rts; ///< RTS Pin mux configuration. Refer to
GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
+ UINT32 Cts; ///< CTS Pin mux configuration. Refer to
GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
+} UART_PIN_MUX;
+
+/**
+ Serial IO UART Controller Configuration
+**/
+typedef struct {
+ SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
+ UART_PIN_MUX PinMux; ///< UART pin mux configuration
+ UINT8 Mode; ///< <b> SerialIoUartPci </b> see
SERIAL_IO_UART_MODE
+ UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART
to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
+ UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b>
Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
+ UINT8 DmaEnable; ///< <b> TRUE </b> Applies to
SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO
mode
+} SERIAL_IO_UART_CONFIG;
+
+typedef enum {
+ SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after
initialization
+/**
+ In mode: SerialIoUartCom;
+ _PS0/_PS3 that supports getting device out of reset
+ In mode: SerialIoUartPci
+ Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
+**/
+ SerialIoUartPgEnabled,
+ SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if
device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
+} SERIAL_IO_UART_PG;
+
+/**
+ Available working modes for SerialIo I2C Host Controller
+
+ 0: SerialIoI2cDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions
on given device
+ are enabled, PSF disabling is skipped. PSF default will
remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions
above 0 in a multifunction device.
+ <b>1: SerialIoI2cPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoI2cHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported
as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to
hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoI2cDisabled,
+ SerialIoI2cPci,
+ SerialIoI2cHidden
+} SERIAL_IO_I2C_MODE;
+
+/**
+ I2C signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_*
in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Sda; ///< SDA Pin mux configuration. Refer to
GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
+ UINT32 Scl; ///< SCL Pin mux configuration. Refer to
GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
+} I2C_PIN_MUX;
+
+/**
+ Serial IO I2C Controller Configuration
+**/
+typedef struct {
+ UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
+ /**
+ I2C Pads Internal Termination.
+ For more information please see Platform Design Guide.
+ Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
+ <b>GpioTermNone: No termination</b>,
+ GpioTermWpu1K: 1kOhm weak pull-up,
+ GpioTermWpu5K: 5kOhm weak pull-up,
+ GpioTermWpu20K: 20kOhm weak pull-up
+ **/
+ UINT8 PadTermination;
+ UINT8 Reserved[2];
+ I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
+} SERIAL_IO_I2C_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_DEVICES_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h
new file mode 100644
index 0000000000..191bd815a1
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h
@@ -0,0 +1,17 @@
+/** @file
+ Silicon Config HOB is used for gathering platform
+ related Intel silicon information and config setting.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_HOB_H_
+#define _SI_CONFIG_HOB_H_
+
+#include <SiPolicyStruct.h>
+
+extern EFI_GUID gSiConfigHobGuid;
+
+// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB
structure.
+typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h
b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h
new file mode 100644
index 0000000000..7b646d8972
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h
@@ -0,0 +1,64 @@
+/** @file
+ Intel reference code configuration policies.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_STRUCT_H_
+#define _SI_POLICY_STRUCT_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/SiPreMemConfig.h>
+#include <ConfigBlock/SiConfig.h>
+
+/**
+ Silicon Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ This member specifies the revision of the Silicon Policy. This field is used
to indicate change
+ to the policy structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_POLICY_REVISION 1
+
+/**
+ Silicon pre-memory Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_PREMEM_POLICY_REVISION 1
+
+
+/**
+ SI Policy PPI in Pre-Mem\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_PREMEM_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of
AddConfigBlock()
+*/
+};
+
+/**
+ SI Policy PPI\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of
AddConfigBlock()
+*/
+};
+
+#endif
--
2.24.0.windows.2
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