Laszlo,
Thanks for the background.
Turns out I was chasing the wrong thing :(. In our tree all MMIO is marked NX
and I was talking a page fault. When I tracked it down I realized it was an
issue with the EFER MSR not getting the NXE (No-Execute Enable) bit set, so any
page table with the NX bit set faults.
I had a bug in my copy of the DXE IPL that was not calling
EnableExecuteDisableBit() so NXE is never set, and that is why I got the page
fault.
Thanks,
Andrew Fish
> On Jul 7, 2020, at 1:21 PM, Laszlo Ersek <ler...@redhat.com> wrote:
>
> On 07/07/20 21:59, Laszlo Ersek wrote:
>
>> (Side note: where I say "synthetic", that does not mean "easy to change"
>> at all. Coming up with good 32-bit and 64-bit MMIO apertures for the
>> PciHostBridgeLib instance was an arduous task. Among other things, this
>> originates from the very quirky placement of the 32-bit address ranges
>> on i440fx and q35 that are usable for PCI MMIO. QEMU doesn't dictate the
>> apertures for the root bridges, but if you allocate an MMIO BAR from an
>> inappropriate address range, you're doomed.)
>
> A key commit regarding the above is 49edde15230a ("OvmfPkg/PlatformPei:
> set 32-bit UC area at PciBase / PciExBarBase (pc/q35)", 2019-06-03).
>
> It was very difficult to find a 32-bit PCI MMIO aperture, facing any
> random guest RAM size, such that we could mark the aperture in
> PlatformPei as UC with no more than the 8 variable MTRRs that QEMU provides.
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=1814
> https://bugzilla.tianocore.org/show_bug.cgi?id=1859
>
> Thanks
> Laszlo
>
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