On Wed, Jun 10, 2020 at 03:47:25 +0530, Wasim Khan wrote:
> From: Wasim Khan <wasim.k...@nxp.com>
>
> Define PCIe related PCDs for LX2160A.
>
> Signed-off-by: Wasim Khan <wasim.k...@nxp.com>
> ---
> Silicon/NXP/LX2160A/LX2160A.dsc.inc | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc
> b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
> index fe8ed402fc4e..43e361464c8e 100644
> --- a/Silicon/NXP/LX2160A/LX2160A.dsc.inc
> +++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
> @@ -38,6 +38,11 @@ [PcdsFixedAtBuild.common]
> gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C0000
>
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x8000000000
This is already provided by LX2160A_PCI1_PHYS_ADDRESS in
Silicon/NXP/LX2160A/Include/Soc.h, and PCI_SEG0_MMIO_MEMBASE would be
better described as an alias of that. Unless the NXP
PciHostBridgeLib/PciSegmentLib is intended to be shared with SoCs
where these base addresses can be different in different platforms.
If so, the PHYS_ADDRESSES would be better defined as derivatives of
PcdPciExp1BaseAddr.
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|6
Is this number possible to be different for different platforms based
on the same SoC?
/
Leif
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
> +
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
>
> --
> 2.7.4
>
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