On Wed, May 20, 2020 at 12:05:03 +0200, Ard Biesheuvel wrote:
> Gary reports that GCC 10 will emit calls to atomics intrinsics routines
> unless -mno-outline-atomics is specified. This means GCC-10 introduces
> new intrinsics, and even though it would be possible to work around this
> by specifying the command line option, this would require a new GCC10
> toolchain profile to be created, which we prefer to avoid.
>
> So instead, add the new intrinsics to our library so they are provided
> when necessary.
>
> Link: https://bugzilla.tianocore.org/show_bug.cgi?id=2723
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@arm.com>
1) Thanks!
2) My head hurts. Is there any chance we could merge the
macro-expanded version?
Of course, this isn't somewhere we expect churn, and this is probably
real handy if we end up having to add more variants, but it feels a
bit write-only at the moment.
If we keep this form, could we sprinkle it with comments a bit? I can
sort of see what it does, but I definitely can't follow it.
/
Leif
> ---
> ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf | 3 +
> ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S | 91
> ++++++++++++++++++++
> 2 files changed, 94 insertions(+)
>
> diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> index d5bad9467758..fcf48c678119 100644
> --- a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> @@ -79,6 +79,9 @@ [Sources.ARM]
> Arm/ldivmod.asm | MSFT
> Arm/llsr.asm | MSFT
>
> +[Sources.AARCH64]
> + AArch64/Atomics.S | GCC
> +
> [Packages]
> MdePkg/MdePkg.dec
> ArmPkg/ArmPkg.dec
> diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S
> b/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S
> new file mode 100644
> index 000000000000..5846131ab19e
> --- /dev/null
> +++ b/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S
> @@ -0,0 +1,91 @@
> +#------------------------------------------------------------------------------
> +#
> +# Copyright (c) 2020, Arm, Limited. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#------------------------------------------------------------------------------
> +
> + .arch armv8-a
> +
> + .macro reg_alias, pfx, sz
> + r0_\sz .req \pfx\()0
> + r1_\sz .req \pfx\()1
> + tmp0_\sz .req \pfx\()16
> + tmp1_\sz .req \pfx\()17
> + .endm
> +
> + .macro fn_start, name:req
> + .section .text.\name
> + .type \name, %function
> +\name\():
> + .endm
> +
> + .macro emit_ld_sz, sz:req, insn:req, opc:req, model:req, s, a,
> l
> + fn_start __aarch64_\insn\()\sz\()\model
> + mov tmp0_\sz, r0_\sz
> +0: ld\a\()xr\s r0_\sz, [x1]
> + .ifnc \insn, swp
> + \opc tmp1_\sz, r0_\sz, tmp0_\sz
> + .else
> + \opc tmp1_\sz, tmp0_\sz
> + .endif
> + st\l\()xr\s w15, tmp1_\sz, [x1]
> + cbnz w15, 0b
> + ret
> + .endm
> +
> + .macro emit_ld, insn:req, opc:req, model:req, a, l
> + emit_ld_sz 1, \insn, \opc, \model, b, \a, \l
> + emit_ld_sz 2, \insn, \opc, \model, h, \a, \l
> + emit_ld_sz 4, \insn, \opc, \model, , \a, \l
> + emit_ld_sz 8, \insn, \opc, \model, , \a, \l
> + .endm
> +
> + .macro emit_cas_sz, sz:req, model:req, uxt:req, s, a, l
> + fn_start __aarch64_cas\sz\()\model
> + \uxt tmp0_\sz, r0_\sz
> +0: ld\a\()xr\s r0_\sz, [x2]
> + cmp r0_\sz, tmp0_\sz
> + bne 1f
> + st\l\()xr\s w15, r1_\sz, [x2]
> + cbnz w15, 0b
> +1: ret
> + .endm
> +
> + .macro emit_cas, model:req, a, l
> + emit_cas_sz 1, \model, uxtb, b, \a, \l
> + emit_cas_sz 2, \model, uxth, h, \a, \l
> + emit_cas_sz 4, \model, mov , , \a, \l
> + emit_cas_sz 8, \model, mov , , \a, \l
> +
> + fn_start __aarch64_cas16\model
> + mov x16, x0
> + mov x17, x1
> +0: ld\a\()xp x0, x1, [x4]
> + cmp x0, x16
> + ccmp x1, x17, #0, eq
> + bne 1f
> + st\l\()xp w15, x16, x17, [x4]
> + cbnz w15, 0b
> +1: ret
> + .endm
> +
> + .macro emit_model, model:req, a, l
> + emit_ld ldadd, add, \model, \a, \l
> + emit_ld ldclr, bic, \model, \a, \l
> + emit_ld ldeor, eor, \model, \a, \l
> + emit_ld ldset, orr, \model, \a, \l
> + emit_ld swp, mov, \model, \a, \l
> + emit_cas \model, \a, \l
> + .endm
> +
> + reg_alias w, 1
> + reg_alias w, 2
> + reg_alias w, 4
> + reg_alias x, 8
> +
> + emit_model _relax
> + emit_model _acq, a
> + emit_model _rel,, l
> + emit_model _acq_rel, a, l
> --
> 2.17.1
>
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