On Fri, Mar 20, 2020 at 20:05:34 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.ban...@nxp.com>
>
> Now the we have added Chassis Package, move the chassis specific common
> code for all SOCs belonging to same chassis to ChassisLib.
>
> Use ChassisLib APIs in SocLib.
>
> Signed-off-by: Pankaj Bansal <pankaj.ban...@nxp.com>
There will be minor API changes required to this file based on
addressing other feedback, but unless any substantial rewrites are
needed:
Reviewed-by: Leif Lindholm <l...@nuviainc.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.inf | 1 +
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 44 -------------
> Silicon/NXP/LS1043A/Include/Soc.h | 6 +-
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 9 ++-
> Silicon/NXP/Library/SocLib/Chassis.c | 61 -------------------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 19 +-----
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 15 +----
> Silicon/NXP/Library/SocLib/NxpChassis.h | 22 -------
> Silicon/NXP/NxpQoriqLs.dec | 6 --
> 10 files changed, 14 insertions(+), 170 deletions(-)
> delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> index 038d48949a39..e522db81e5c0 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -24,6 +24,7 @@ [Packages]
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> diff --git
> a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 7a43ad86d183..07ca6b34445f 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -19,6 +19,7 @@ [Packages]
> ArmPlatformPkg/ArmPlatformPkg.dec
> EmbeddedPkg/EmbeddedPkg.dec
> MdePkg/MdePkg.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> deleted file mode 100644
> index 3f00a2614131..000000000000
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -/** Soc.h
> -* Header defining the Base addresses, sizes, flags etc for chassis 1
> -*
> -* Copyright 2017-2020 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef NXP_SOC_H_
> -#define NXP_SOC_H_
> -
> -#define CLK_FREQ 100000000
> -
> -#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> -
> -/* SMMU Defintions */
> -#define SMMU_BASE_ADDR 0x09000000
> -#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> -#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> -#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> -#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> -#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> -
> -#define SCR0_USFCFG_MASK 0x00000400
> -#define SCR0_CLIENTPD_MASK 0x00000001
> -#define SACR_PAGESIZE_MASK 0x00010000
> -#define IDR1_PAGESIZE_MASK 0x80000000
> -
> -/* Device Configuration and Pin Control */
> -typedef struct {
> - UINT8 Res0[0x100-0x00];
> - UINT32 RcwSr[16]; /* Reset control word status */
> -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> -} CCSR_GUR;
> -
> -UINT32
> -EFIAPI
> -GurRead (
> - IN UINTN Address
> - );
> -
> -#endif /* NXP_SOC_H_ */
> diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> b/Silicon/NXP/LS1043A/Include/Soc.h
> index e62de570da8a..97a77d3f5da6 100644
> --- a/Silicon/NXP/LS1043A/Include/Soc.h
> +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> @@ -8,7 +8,7 @@
> #ifndef SOC_H__
> #define SOC_H__
>
> -#include <Chassis2/NxpSoc.h>
> +#include <Chassis.h>
>
> /**
> Soc Memory Map
> @@ -43,13 +43,13 @@
> #define LS1043A_I2C_SIZE 0x10000
> #define LS1043A_I2C_NUM_CONTROLLERS 4
>
> -#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS
> +#define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
>
> /**
> Reset Control Word (RCW) Bits
> **/
> #define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
>
> -typedef CCSR_GUR LS1043A_DEVICE_CONFIG;
> +typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
>
> #endif // SOC_H__
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index 6239cfe761e6..7e75d5b7cba9 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -7,6 +7,8 @@
> #
> #
>
> +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
> +
> [LibraryClasses.common]
>
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
> SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -29,9 +31,6 @@ [PcdsFixedAtBuild.common]
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
>
> - #
> - # Big Endian IPs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> -
> +[PcdsFeatureFlag]
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> ##
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c
> b/Silicon/NXP/Library/SocLib/Chassis.c
> deleted file mode 100644
> index 90677f0f36ca..000000000000
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ /dev/null
> @@ -1,61 +0,0 @@
> -/** @file
> - SoC specific Library containg functions to initialize various SoC
> components
> -
> - Copyright 2017-2020 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#ifdef CHASSIS2
> -#include <Chassis2/NxpSoc.h>
> -#elif CHASSIS3
> -#include <Chassis3/NxpSoc.h>
> -#endif
> -#include <Library/ArmSmcLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoAccessLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PrintLib.h>
> -#include <Library/SerialPortLib.h>
> -
> -#include "NxpChassis.h"
> -
> -UINT32
> -EFIAPI
> -GurRead (
> - IN UINTN Address
> - )
> -{
> - if (FixedPcdGetBool (PcdGurBigEndian)) {
> - return SwapMmioRead32 (Address);
> - } else {
> - return MmioRead32 (Address);
> - }
> -}
> -
> -/*
> - * Setup SMMU in bypass mode
> - * and also set its pagesize
> - */
> -VOID
> -SmmuInit (
> - VOID
> - )
> -{
> - UINT32 Value;
> -
> - /* set pagesize as 64K and ssmu-500 in bypass mode */
> - Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> - MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> -
> - Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) &
> ~SCR0_USFCFG_MASK;
> - MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> -
> - Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) &
> ~SCR0_USFCFG_MASK;
> - MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> -}
> -
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index b14ada7f595d..a50c072e84d5 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -8,16 +8,8 @@
> **/
>
> #include <Base.h>
> -#include <NxpChassis.h>
> -#include <Chassis2/NxpSoc.h>
> -#include <Library/BaseLib.h>
> -#include <Library/BaseMemoryLib.h>
> +#include <Library/ChassisLib.h>
> #include <Library/DebugLib.h>
> -#include <Library/IoAccessLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PrintLib.h>
> -#include <Library/SerialPortLib.h>
> #include <Library/SocLib.h>
> #include <Soc.h>
>
> @@ -61,7 +53,7 @@ SocGetClock (
> switch (ClockType) {
> case NXP_UART_CLOCK:
> case NXP_I2C_CLOCK:
> - RcwSr = GurRead ((UINTN)&Dcfg->RcwSr[0]);
> + RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
> ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
> break;
> default:
> @@ -79,12 +71,7 @@ SocInit (
> VOID
> )
> {
> - SmmuInit ();
> -
> - //
> - // Early init serial Port to get board information.
> - //
> - SerialPortInitialize ();
> + ChassisInit ();
>
> return;
> }
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index bb15e0a3d710..1d042bbfc4e4 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -14,25 +14,14 @@ [Defines]
> LIBRARY_CLASS = SocLib
>
> [Packages]
> - ArmPkg/ArmPkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> - BaseLib
> + ChassisLib
> DebugLib
> - IoAccessLib
> - SerialPortLib
>
> [Sources.common]
> - Chassis.c
> Chassis2/Soc.c
> -
> -[BuildOptions]
> - GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> -
> -[FixedPcd]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h
> b/Silicon/NXP/Library/SocLib/NxpChassis.h
> deleted file mode 100644
> index 836df103f80f..000000000000
> --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/** @file
> -* Header defining the Base addresses, sizes, flags etc for chassis 1
> -*
> -* Copyright 2017-2020 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef NXP_CHASSIS_H_
> -#define NXP_CHASSIS_H_
> -
> -/*
> - * Setup SMMU in bypass mode
> - * and also set its pagesize
> - */
> -VOID
> -SmmuInit (
> - VOID
> - );
> -
> -#endif /* NXP_CHASSIS_H_ */
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 3e79f502c127..71e43c1ffd86 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -24,12 +24,6 @@ [Guids.common]
> gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5,
> 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e,
> 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
>
> -[PcdsFixedAtBuild.common]
> - #
> - # Pcds to support Big Endian IPs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> -
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
> --
> 2.17.1
>
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