Reviewed-by: Chasel Chiu <chasel.c...@intel.com>
> -----Original Message----- > From: Esakkithevar, Kathappan <kathappan.esakkithe...@intel.com> > Sent: Wednesday, February 12, 2020 3:13 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaga...@intel.com>; Chiu, Chasel > <chasel.c...@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desim...@intel.com>; Kethi Reddy, Deepika > <deepika.kethi.re...@intel.com>; Agyeman, Prince > <prince.agye...@intel.com> > Subject: [edk2-platforms] [PATCH v2 2/7] > CometlakeOpenBoardPkg/CometlakeURvp: Add headers > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280 > > Header files for the CometlakeURvp board instance. > > Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithe...@intel.com> > Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> > Cc: Chasel Chiu <chasel.c...@intel.com> > Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> > Cc: Deepika Kethi Reddy <deepika.kethi.re...@intel.com> > Cc: Prince Agyeman <prince.agye...@intel.com> > --- > .../CometlakeURvp/Include/Fdf/FlashMapInclude.fdf | 49 ++++++++ > .../CometlakeURvp/Include/PeiPlatformHookLib.h | 131 > +++++++++++++++++++++ > .../CometlakeURvp/Include/PeiPlatformLib.h | 40 +++++++ > .../CometlakeURvp/Include/PlatformBoardConfig.h | 105 > +++++++++++++++++ > .../CometlakeURvp/Include/PlatformInfo.h | 44 +++++++ > 5 files changed, 369 insertions(+) > create mode 100644 > Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashM > apInclude.fdf > create mode 100644 > Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatform > HookLib.h > create mode 100644 > Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatform > Lib.h > create mode 100644 > Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformBo > ardConfig.h > create mode 100644 > Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformInf > o.h > > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flash > MapInclude.fdf > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flash > MapInclude.fdf > new file mode 100644 > index 0000000000..d9959a79d0 > --- /dev/null > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Fla > +++ shMapInclude.fdf > @@ -0,0 +1,49 @@ > +## @file > +# FDF file for the CometlakeURvp board. > +# > +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +#============================================================== > ======== > +===========# > +# 8 M BIOS - for FSP wrapper > +#============================================================== > ===================# > +DEFINE FLASH_BASE > = 0xFF800000 # > +DEFINE FLASH_SIZE > = 0x00800000 # > +DEFINE FLASH_BLOCK_SIZE > = 0x00010000 # > +DEFINE FLASH_NUM_BLOCKS > = 0x00000080 # > +#============================================================== > ======== > +===========# > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset > = 0x00000000 # Flash addr (0xFF800000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize > = 0x00040000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = > 0x00000000 # Flash addr (0xFF800000) > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > = 0x0001E000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset > = > +0x0001E000 # Flash addr (0xFF81E000) SET > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = > 0x00002000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset > = 0x00020000 # Flash addr (0xFF820000) > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > = 0x00020000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset > = 0x00040000 # Flash addr (0xFF840000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize > = 0x00050000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = > 0x00090000 # Flash addr (0xFF890000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = > 0x00070000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset > = 0x00100000 # Flash addr (0xFF900000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize > = 0x00090000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset > = 0x00190000 # Flash addr (0xFF990000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize > = 0x00190000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset > = 0x00320000 # Flash addr (0xFFB20000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize > = 0x00170000 # > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > = 0x00490000 # Flash addr (0xFFC90000) > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > = 0x000B0000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset > = 0x00540000 # Flash addr (0xFFD40000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize > = 0x00070000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset > = 0x005B0000 # Flash addr (0xFFDB0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize > = 0x000EC000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset > = 0x0069C000 # Flash addr (0xFFE9C000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize > = 0x00014000 # > +SET > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = > 0x006B0000 # Flash addr (0xFFEB0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize > = 0x00010000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset > = 0x006C0000 # Flash addr (0xFFEC0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize > = 0x00140000 # > + > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfor > mHookLib.h > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfo > rmHookLib.h > new file mode 100644 > index 0000000000..690054d2e9 > --- /dev/null > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlat > +++ formHookLib.h > @@ -0,0 +1,131 @@ > +/** @file > + > + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _PEI_PLATFORM_HOOK_LIB_H_ > +#define _PEI_PLATFORM_HOOK_LIB_H_ > + > +#include <PlatformInfo.h> > +#include <Library/PeiServicesLib.h> > +#include <Library/GpioLib.h> > + > + > +//EC Command to provide one byte of debug indication #define > +BSSB_DEBUG_INDICATION 0xAE > +/** > + Configure EC for specific devices > + > + @param[in] PchLan - The PchLan of PCH_SETUP variable. > + @param[in] BootMode - The current boot mode. > +**/ > +VOID > +EcInit ( > + IN UINT8 PchLan, > + IN EFI_BOOT_MODE BootMode > + ); > + > +/** > + Checks if Premium PMIC present > + > + @retval TRUE if present > + @retval FALSE it discrete/other PMIC **/ BOOLEAN > +IsPremiumPmicPresent ( > + VOID > + ); > + > +/** > + Pmic Programming to supprort LPAL Feature > + > + @retval NONE > +**/ > +VOID > +PremiumPmicDisableSlpS0Voltage ( > + VOID > + ); > + > +/** > +Pmic Programming to supprort LPAL Feature > + @retval NONE > +**/ > +VOID > +PremiumPmicEnableSlpS0Voltage( > + VOID > + ); > + > +/** > + Do platform specific programming pre-memory. For example, EC init, > +Chipset programming > + > + @retval Status > +**/ > +EFI_STATUS > +PlatformSpecificInitPreMem ( > + VOID > + ); > + > +/** > + Do platform specific programming post-memory. > + > + @retval Status > +**/ > +EFI_STATUS > +PlatformSpecificInit ( > + VOID > + ); > + > +/** > + Configure GPIO and SIO Before Memory is ready. > + > + @retval EFI_SUCCESS Operation success. > +**/ > +EFI_STATUS > +BoardInitPreMem ( > + VOID > + ); > + > +/** > + Configure GPIO and SIO > + > + @retval EFI_SUCCESS Operation success. > +**/ > +EFI_STATUS > +BoardInit ( > + VOID > + ); > + > +/** > +Voltage Margining Routine > + > +@retval EFI_SUCCESS Operation success > +**/ > +EFI_STATUS > +VoltageMarginingRoutine( > + VOID > + ); > + > +/** > + Detect recovery mode > + > + @retval EFI_SUCCESS System in Recovery Mode > + @retval EFI_UNSUPPORTED System doesn't support Recovery Mode > + @retval EFI_NOT_FOUND System is not in Recovery Mode > +**/ > +EFI_STATUS > +IsRecoveryMode ( > + VOID > + ); > + > +/** > + Early board Configuration before Memory is ready. > + > + @retval EFI_SUCCESS Operation success. > +**/ > +EFI_STATUS > +BoardInitEarlyPreMem ( > + VOID > + ); > +#endif > + > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfor > mLib.h > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfo > rmLib.h > new file mode 100644 > index 0000000000..3443479a52 > --- /dev/null > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlat > +++ formLib.h > @@ -0,0 +1,40 @@ > +/** @file > + > + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _PEI_PLATFORM_LIB_H_ > +#define _PEI_PLATFORM_LIB_H_ > + > + > + > +#define PEI_DEVICE_DISABLED 0 > +#define PEI_DEVICE_ENABLED 1 > + > +typedef struct { > + UINT8 Register; > + UINT32 Value; > +} PCH_GPIO_DEV; > + > +// > +// GPIO Initialization Data Structure > +// > +typedef struct{ > + PCH_GPIO_DEV Use_Sel; > + PCH_GPIO_DEV Use_Sel2; > + PCH_GPIO_DEV Use_Sel3; > + PCH_GPIO_DEV Io_Sel; > + PCH_GPIO_DEV Io_Sel2; > + PCH_GPIO_DEV Io_Sel3; > + PCH_GPIO_DEV Lvl; > + PCH_GPIO_DEV Lvl2; > + PCH_GPIO_DEV Lvl3; > + PCH_GPIO_DEV Inv; > + PCH_GPIO_DEV Blink; > + PCH_GPIO_DEV Rst_Sel; > + PCH_GPIO_DEV Rst_Sel2; > +} GPIO_INIT_STRUCT; > + > +#endif > + > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platform > BoardConfig.h > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platform > BoardConfig.h > new file mode 100644 > index 0000000000..4d286b897a > --- /dev/null > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platfor > +++ mBoardConfig.h > @@ -0,0 +1,105 @@ > +/** @file > + Header file for Platform Boards Configurations. > + > + > + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _PLATFORM_BOARD_CONFIG_H > +#define _PLATFORM_BOARD_CONFIG_H > + > +#include <ConfigBlock.h> > +#include <PchPolicyCommon.h> > +#include <ConfigBlock/MemoryConfig.h> > +#include <GpioConfig.h> > +#include <TbtBoardInfo.h> > + > +#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1) > +#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16) & > 0xFFF0)) > + > +#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001 > #define > +BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001 #define > +BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001 #define > +BOARD_NO_BATTERY_SUPPORT 0 #define > BOARD_REAL_BATTERY_SUPPORTED BIT0 > +#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1 > + > +#pragma pack(1) > + > +typedef struct { > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 > Config Block Header > +} BOARD_CONFIG_BLOCK; > + > +typedef struct { > + UINT8 GpioSupport; > + UINT32 WakeGpioNo; > + UINT8 HoldRstExpanderNo; > + UINT32 HoldRstGpioNo; > + BOOLEAN HoldRstActive; > + UINT8 PwrEnableExpanderNo; > + UINT32 PwrEnableGpioNo; > + BOOLEAN PwrEnableActive; > +} SWITCH_GRAPHIC_GPIO; > + > +typedef struct { > + UINT8 ClkReqNumber : 4; > + UINT8 ClkReqSupported : 1; > + UINT8 DeviceResetPadActiveHigh : 1; > + UINT32 DeviceResetPad; > +} ROOT_PORT_CLK_INFO; > + > +typedef struct { > + UINT8 Section; > + UINT8 Pin; > +} EXPANDER_GPIO_CONFIG; > + > +typedef enum { > + BoardGpioTypePch, > + BoardGpioTypeExpander, > + BoardGpioTypeNotSupported = 0xFF > +} BOARD_GPIO_TYPE; > + > +typedef struct { > + UINT8 Type; > + UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG > + union { > + UINT32 Pin; > + EXPANDER_GPIO_CONFIG Expander; > + } u; > +} BOARD_GPIO_CONFIG; > + > +// Do not change the encoding. It must correspond with > PCH_PCIE_CLOCK_USAGE from PCH RC. > +#define NOT_USED 0xFF > +#define FREE_RUNNING 0x80 > +#define LAN_CLOCK 0x70 > +#define PCIE_PEG 0x40 > +#define PCIE_PCH 0x00 > + > +typedef struct { > + UINT32 ClockUsage; > + UINT32 ClkReqSupported; > +} PCIE_CLOCK_CONFIG; > + > +typedef union { > + UINT64 Blob; > + BOARD_GPIO_CONFIG BoardGpioConfig; > + ROOT_PORT_CLK_INFO Info; > + PCIE_CLOCK_CONFIG PcieClock; > +} PCD64_BLOB; > + > +typedef union { > + UINT32 Blob; > + USB20_AFE Info; > +} PCD32_BLOB; > + > +#ifndef IO_EXPANDER_DISABLED > +#define IO_EXPANDER_DISABLED 0xFF > +#endif > + > +#define SPD_DATA_SIZE 512 > + > +#pragma pack() > + > +#endif // _PLATFORM_BOARD_CONFIG_H > + > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformI > nfo.h > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformI > nfo.h > new file mode 100644 > index 0000000000..f8854485b4 > --- /dev/null > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platfor > +++ mInfo.h > @@ -0,0 +1,44 @@ > +/** @file > + GUID used for Platform Info Data entries in the HOB list. > + > + > + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _PLATFORM_INFO_H_ > +#define _PLATFORM_INFO_H_ > + > +#pragma pack(1) > + > +/// > +/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in > +GpioConfig.h /// typedef UINT32 PCH_GPIO_PAD; //Copied from > +GpioConfig.h (need to change it based on include) > + > +typedef struct { > +UINT8 Expander; > +UINT8 Pin; > +UINT16 Reserved; // Reserved for future use > +} IO_EXPANDER_PAD; > + > +typedef union { > +PCH_GPIO_PAD PchGpio; > +IO_EXPANDER_PAD IoExpGpio; > +} GPIO_PAD_CONFIG; > + > +typedef struct { > +UINT8 GpioType; // 0: Disabled (no GPIO support), 1: > PCH, 2: I/O Expander > +UINT8 Reserved[3]; // Reserved for future use > +GPIO_PAD_CONFIG GpioData; > +} PACKED_GPIO_CONFIG; > + > +typedef union { > +PACKED_GPIO_CONFIG PackedGpio; > +UINT64 Data64; > +} COMMON_GPIO_CONFIG; > + > +#pragma pack() > + > +#endif > + > -- > 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54239): https://edk2.groups.io/g/devel/message/54239 Mute This Topic: https://groups.io/mt/71175623/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
