Add LX2160A SocLib
Signed-off-by: Pankaj Bansal <pankaj.ban...@nxp.com>
---
Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h | 39 +++++++++
Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec | 23 ++++++
.../NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc | 34 ++++++++
.../LX2160A/Library/SocLib/SocLib.c | 79 +++++++++++++++++++
.../LX2160A/Library/SocLib/SocLib.inf | 31 ++++++++
5 files changed, 206 insertions(+)
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
b/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
new file mode 100644
index 0000000000..cc1f91272d
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#include <Chassis.h>
+
+/**
+ Soc Memory Map
+**/
+#define LX2160A_CCSR_PHYS_ADDRESS 0x1000000
+#define LX2160A_CCSR_SIZE 0xF000000
+
+#define LX2160A_FLEXSPI_PHYS_ADDRESS 0x20000000
+#define LX2160A_FLEXSPI_SIZE SIZE_256MB
+
+#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
+
+#define LX2160A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LX2160A_DRAM0_SIZE SIZE_2GB
+#define LX2160A_DRAM1_PHYS_ADDRESS 0x2080000000
+#define LX2160A_DRAM1_SIZE 0x1F80000000 // 128 GB
+
+#define LX2160A_I2C0_PHYS_ADDRESS 0x2000000
+
+/**
+ Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
+
+#endif
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
new file mode 100644
index 0000000000..f786a57ebc
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
@@ -0,0 +1,34 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
+ SerialPortLib|Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
+
+[PcdsFixedAtBuild.common]
+## PL011 Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|16
+
+[PcdsDynamicDefault.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x20000000
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6200000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0c0c0000
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
new file mode 100644
index 0000000000..2c19c72b5f
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
@@ -0,0 +1,79 @@
+/** @file
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ **/
+#include <Soc.h>
+#include <Library/ChassisLib.h>
+#include <Library/SocLib.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider
values to be applied
+ to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is
to be applied.
+ @param[in] ClockType IP modules whose clock value is to be retrieved
+ @param[in] Args Variable Args lists that is parsed based on the
ClockType
+ e.g. if there are multiple modules of same type then
this value tells the
+ instance of module for which clock is to be retrieved.
+ (e.g. if there are four i2c controllers in SOC, then
this value can be 1, 2, 3, 4)
+ for IP modules which have only single instance in SOC
(e.g. one QSPI controller)
+ this value can be null (i.e. no arg)
+
+ @return > 0 Return the input clock frequency to an IP Module
+ 0 either IP module doesn't exist in SOC
+ or IP module instance doesn't exist in SOC
+ or IP module instance is disabled. i.e. no input clock is
provided to IP module instance.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN UINT32 ClockType,
+ IN VA_LIST Args
+ )
+{
+ LX2160A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LX2160A_DEVICE_CONFIG *)LX2160A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 3; // platform pll / 8
+ break;
+ case NXP_I2C_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 4; // platform pll / 16
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ ChassisInit ();
+
+ return;
+}
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
new file mode 100644
index 0000000000..ea9d45a021
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
@@ -0,0 +1,31 @@
+#@file
+#
+# Component description file for SocLib module
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = SocLib
+ FILE_GUID = 9b046753-2b4f-42d8-bfb3-468892fe17d4
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Sources.common]
+ SocLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+ Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
+
+[LibraryClasses]
+ ChassisLib
--
2.17.1
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