Current ASSERT logic checks that the EISS bit is still
set after we clear it. This is incorrect, it should be
checking that that the EISS bit is clear after we clear it.
Cc: Chasel Chiu <chasel.c...@intel.com>
Cc: Michael Kubacki <michael.a.kuba...@intel.com>
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
---
.../Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
index aadc367a9f..c34c378de2 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
@@ -184,7 +184,7 @@ DisableBiosWriteProtect (
B_PCH_SPI_BC_WPD
);
- ASSERT ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) &
B_PCH_SPI_BC_EISS) != 0);
+ ASSERT ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) &
B_PCH_SPI_BC_EISS) == 0);
return EFI_SUCCESS;
}
--
2.23.0.windows.1
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