MdeModulePkg/SdMmcHcDxe update to use rev 3 of SdMmcOverrideProtocol
reworked SD card initialization and added new enums describing lower
speeds. Include this in XenonDxe, which fixes Armada70x0Db SD interface.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c
b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c
index 7bfe240..6059cf8 100755
--- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c
+++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c
@@ -360,6 +360,8 @@ XenonPhySlowMode (
if (((Timing == SdMmcUhsSdr50) ||
(Timing == SdMmcUhsSdr25) ||
(Timing == SdMmcUhsSdr12) ||
+ (Timing == SdMmcSdDs) ||
+ (Timing == SdMmcSdHs) ||
(Timing == SdMmcMmcHsDdr) ||
(Timing == SdMmcMmcHsSdr) ||
(Timing == SdMmcMmcLegacy)) && SlowMode) {
@@ -396,7 +398,7 @@ XenonSetPhy (
Var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
XenonHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL1, FALSE,
SDHC_REG_SIZE_4B, &Var);
- if (Timing == SdMmcUhsSdr12) {
+ if (Timing == SdMmcUhsSdr12 || Timing == SdMmcSdDs) {
if (SlowMode) {
XenonHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE,
SDHC_REG_SIZE_4B, &Var);
Var |= QSN_PHASE_SLOW_MODE_BIT;
@@ -749,7 +751,7 @@ XenonInit (
// Set lowest clock and the PHY for the initialization phase
XenonSetClk (PciIo, XENON_MMC_BASE_CLK);
- Status = XenonSetPhy (PciIo, SlowMode, TuningStepDivisor, SdMmcUhsSdr12);
+ Status = XenonSetPhy (PciIo, SlowMode, TuningStepDivisor, SdMmcSdDs);
if (EFI_ERROR (Status)) {
return Status;
}
--
2.7.4
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