> -----Original Message----- > From: Albecki, Mateusz > Sent: Thursday, September 26, 2019 10:28 PM > To: devel@edk2.groups.io > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas > Subject: [PATCHv2 0/3] Fix eMMC bus timing switch issue > > SD host controller specification section 3.9 recommends that controller's bus > timing > should be switched after card's bus timing has been switched. In current > eMMC > driver implementation every host controller switch has been done before call > to > EmmcSwitchBusTiming which is causing issues on some eMMC controllers. > > In HS200 switch sequence we removed stopping and starting the SD clock > when > switching the host controller timing. Stopping the clock before bus timing > switch is only neccessary if preset value enable is set in host controller. > Current code doesn't check if this field is enabled or doesn't support > this feature for any other bus timing change so it has been removed. > > Third patch fixes issue with switch to SdMmcMmcLegacy speed mode that > was > introduced when we implemented v3 of override protocol. In new flow we > allowed > EmmcSwitchToHighSpeed to be called with SdMmcMmcLegacy since all of > the logic > in that function is ready to service this speed mode. > > Tests performed on patch series v1: > - eMMC enumeration and OS boot in HS400 > - eMMC enumeration and OS boot in HS200 > - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz > > Tests have been performed on 2 eMMC host controllers. One that has been > failing > with old driver and one that has been passing with old driver. Both > controllers > pass all tests with multiple eMMC devices used. > > Note: We were unable to test DDR speed mode because on test machines > both new flow > and old flow was failing with this speed. I suspect it is a hardware problem. > > Tests performed on patch series v2: > -eMMC enumeration and OS boot in backwards compatible legacy timing. > > Performed on single host controller and 2 eMMC devices(Samsung and > SanDisk) > > Cc: Hao A Wu <hao.a...@intel.com> > Cc: Marcin Wojtas <m...@semihalf.com>
For the embedded eMMC on Intel Leaf Hill board, all of the below bus timing modes are verified: HS400 HS200 High Speed DDR High Speed SDR Legacy MMC For the series, Reviewed-by: Hao A Wu <hao.a...@intel.com> Tested-by: Hao A Wu <hao.a...@intel.com> I will wait for comments from Marcin before pushing this series. Best Regards, Hao Wu > > Albecki, Mateusz (3): > MdeModulePkg/SdMmcPciHcDxe: Remove clock stop and start from HS200 > switch > MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence > MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing > handling > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 107 ++++++++-- > -------------- > 1 file changed, 33 insertions(+), 74 deletions(-) > > -- > 2.14.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48181): https://edk2.groups.io/g/devel/message/48181 Mute This Topic: https://groups.io/mt/34299251/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
