Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
-----Original Message-----
From: Agyeman, Prince
Sent: Monday, September 9, 2019 4:15 PM
To: devel@edk2.groups.io
Cc: Wei, David Y <david.y....@intel.com>; Gao, Liming <liming....@intel.com>;
Sinha, Ankit <ankit.si...@intel.com>; Agyeman, Prince
<prince.agye...@intel.com>; Kubacki, Michael A <michael.a.kuba...@intel.com>;
Desimone, Nathaniel L <nathaniel.l.desim...@intel.com>
Subject: [edk2-platforms] [PATCH 3/3] SimicsIch10Pkg: Fix GCC build issues
Cc: David Wei <david.y....@intel.com>
Cc: Liming Gao <liming....@intel.com>
Cc: Ankit Sinha <ankit.si...@intel.com>
Cc: Agyeman Prince <prince.agye...@intel.com>
Cc: Kubacki Michael A <michael.a.kuba...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Signed-off-by: Prince Agyeman <prince.agye...@intel.com>
---
.../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 3 ---
.../SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c | 7 ++-----
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git
a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c
b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c
index bd08b2453b..3e7dffedfb 100644
---
a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c
+++ b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/Sp
+++ iCommon.c
@@ -637,7 +637,6 @@ SendSpiCmd (
EFI_STATUS Status;
UINT32 Index;
SPI_INSTANCE *SpiInstance;
- UINTN SpiBaseAddress;
UINTN PchSpiBar0;
UINT32 HardwareSpiAddr;
UINT32 FlashRegionSize;
@@ -648,9 +647,7 @@ SendSpiCmd (
Status = EFI_SUCCESS;
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
- SpiBaseAddress = SpiInstance->PchSpiBase;
PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
- SpiBaseAddress = SpiInstance->PchSpiBase;
ABase = SpiInstance->PchAcpiBase;
//
diff --git
a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c
b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c
index 268b04d25a..cc2d00b785 100644
--- a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c
+++ b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.
+++ c
@@ -131,7 +131,6 @@ SmmControl2DxeTrigger (
IN UINTN ActivationInterval OPTIONAL
)
{
- EFI_STATUS Status;
//
// No support for queued or periodic activation.
//
@@ -141,7 +140,7 @@ SmmControl2DxeTrigger (
///
/// Clear any pending the APM SMI
///
- Status = SmmClear();
+ SmmClear();
//
// The so-called "Advanced Power Management Status Port Register" is in fact
// a generic data passing register, between the caller and the SMI @@ -181,8
+180,6 @@ SmmControl2DxeClear (
IN BOOLEAN Periodic OPTIONAL
)
{
- EFI_STATUS Status;
-
if (Periodic) {
return EFI_INVALID_PARAMETER;
}
@@ -201,7 +198,7 @@ SmmControl2DxeClear (
//
// So, nothing to do here.
//
- Status = SmmClear();
+ SmmClear();
return EFI_SUCCESS;
}
--
2.19.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#47099): https://edk2.groups.io/g/devel/message/47099
Mute This Topic: https://groups.io/mt/34086416/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
