REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150
V2 changes:
Add xchg 16 bit instructions to handle sgdt and sidt base
63:48 bits and 47:32 bits.
Add comment to explain why xchg 64bit isnt being used
Fix #AC split lock's caused by seperating base and limit from sgdt
and sidt by changing xchg operands to 32-bit to stop from crossing
cacheline.
Signed-off-by: John E Lofgren <john.e.lofg...@intel.com>
---
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 20
++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
index 4db1a09f28..7b7642b290 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
@@ -180,21 +180,29 @@ HasErrorCode:
push qword [rbp + 24]
;; UINT64 Gdtr[2], Idtr[2];
+ ; sidt and sgdt saves 10 bytes to memory, 8 bytes = base and 2 bytes =
limit.
+ ; To avoid #AC split lock when separating base and limit into their
+ ; own separate 64 bit memory, we can’t use 64 bit xchg since base [63:48]
bits
+ ; may cross the cache line.
xor rax, rax
push rax
push rax
sidt [rsp]
- xchg rax, [rsp + 2]
- xchg rax, [rsp]
- xchg rax, [rsp + 8]
+ xchg eax, [rsp + 2]
+ xchg eax, [rsp]
+ xchg eax, [rsp + 8]
+ xchg ax, [rsp + 6]
+ xchg ax, [rsp + 4]
xor rax, rax
push rax
push rax
sgdt [rsp]
- xchg rax, [rsp + 2]
- xchg rax, [rsp]
- xchg rax, [rsp + 8]
+ xchg eax, [rsp + 2]
+ xchg eax, [rsp]
+ xchg eax, [rsp + 8]
+ xchg ax, [rsp + 6]
+ xchg ax, [rsp + 4]
;; UINT64 Ldtr, Tr;
xor rax, rax
--
2.16.2.windows.1
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