Reviewed-by: Chasel Chiu <chasel.c...@intel.com>
> -----Original Message----- > From: Kubacki, Michael A > Sent: Saturday, August 17, 2019 8:16 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaga...@intel.com>; Chiu, Chasel > <chasel.c...@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desim...@intel.com>; Gao, Liming <liming....@intel.com>; > Kinney, Michael D <michael.d.kin...@intel.com>; Sinha, Ankit > <ankit.si...@intel.com> > Subject: [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package > DSC files > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082 > > Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> > Cc: Chasel Chiu <chasel.c...@intel.com> > Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> > Cc: Liming Gao <liming....@intel.com> > Cc: Michael D Kinney <michael.d.kin...@intel.com> > Cc: Ankit Sinha <ankit.si...@intel.com> > Signed-off-by: Michael Kubacki <michael.a.kuba...@intel.com> > --- > Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 215 > ++++++++++++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc | 130 > ++++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc | 69 +++++++ > Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc | 33 +++ > Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc | 37 ++++ > Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc | 21 ++ > Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc | 44 ++++ > 7 files changed, 549 insertions(+) > > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc > b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc > new file mode 100644 > index 0000000000..37c77d8f63 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc > @@ -0,0 +1,215 @@ > +## @file > +# Component description file for the Coffee Lake silicon package DSC file. > +# > +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[PcdsFeatureFlag] > +gSiPkgTokenSpaceGuid.PcdTraceHubEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdSiCsmEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdUseHpetTimer |TRUE > +gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdAcpiEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE > +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdIpuEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdGnaEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdSaOcEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdCflCpuEnable |FALSE > +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE > +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE > + > +[PcdsFixedAtBuild.common] > +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 > +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000 > + > + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |10 > + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |18 > + > +[PcdsDynamicDefault.common] > +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000 > + > +## Specifies the AP wait loop state during POST phase. > +# The value is defined as below. > +# 1: Place AP in the Hlt-Loop state. > +# 2: Place AP in the Mwait-Loop state. > +# 3: Place AP in the Run-Loop state. > +# @Prompt The AP wait loop state. > +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 > +## Specifies the AP target C-state for Mwait during POST phase. > +# The default value 0 means C1 state. > +# The value is defined as below.<BR><BR> # @Prompt The specified AP > +target C-state for Mwait. > +gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 > + > +[Defines] > + PLATFORM_NAME = CoffeelakeSiliconPkg > + PLATFORM_GUID = A45CA44C-AB04-4932-A77C-5A7179F66A22 > + PLATFORM_VERSION = 0.4 > + DSC_SPECIFICATION = 0x00010005 > + OUTPUT_DIRECTORY = Build/CoffeelakeSiliconPkg > + SUPPORTED_ARCHITECTURES = IA32|X64 > + BUILD_TARGETS = DEBUG|RELEASE > + SKUID_IDENTIFIER = DEFAULT > + > + DEFINE PLATFORM_SI_PACKAGE = CoffeelakeSiliconPkg > + > + # > + # Definition for Build Flag > + # > + !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc > + > +[LibraryClasses.common] > + # > + # Entry point > + # > + > +PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.i > n > +f > + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf > + > +DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint > .in > +f > + > +UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntr > +yPoint.inf > + > +UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/Uefi > +ApplicationEntryPoint.inf > + > +PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BaseP > e > +CoffExtraActionLibNull.inf > + > + # > + # Basic > + # > + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf > + > + > BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRe > pStr.i > + nf PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf > + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > + > + > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci > + .inf > + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf > + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > + > + > CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac > heMa > + intenanceLib.inf > + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > + > + > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BaseP > + eCoffGetEntryPointLib.inf > + # > + # UEFI & PI > + # > + > + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiB > + ootServicesTableLib.inf > + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib > + /UefiRuntimeServicesTableLib.inf > + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf > + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf > + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf > + > + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibId > + t/PeiServicesTablePointerLibIdt.inf > + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf > + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf > + > + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTabl > + eLib.inf > + > + > + S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScrip > + tLibNull.inf S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf > + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf > + > + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf > + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf > + > + > SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroni > + zationLib.inf > + > + > + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/Bas > + eDebugPrintErrorLevelLib.inf > + > SmiHandlerProfileLib|Edk2/MdePkg/Library/SmiHandlerProfileLibNull/SmiH > + andlerProfileLibNull.inf > + > + # > + # Misc > + # > + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf > + > + > PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformance > Li > + bNull.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > + > + > TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemp > l > + ate.inf > + > PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDeb > ug.i > + nf > + > ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseR > ep > + ortStatusCodeLibNull.inf > + MtrrLib|ClientSiliconPkg/Override/UefiCpuPkg/Library/MtrrLib/MtrrLib.i > + nf # CSPO-0012: RoyalParkOverrideContent > + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf > + > +############################################################### > ######## > +############################## > + > +# > +# Silicon Init Common Library > +# > +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc > +ConfigBlockLib|ClientSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBl > +ConfigBlockLib|ockLib.inf > +PchTraceHubInitLib|ClientSiliconPkg/Library/BasePchTraceHubInitLib/Base > +PchTraceHubInitLib|PchTraceHubInitLib.inf > + > +[LibraryClasses.IA32] > +# > +# PEI phase common > +# > + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf > + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf > + > +MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemor > yAllo > +cationLib.inf > + > +ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiE > x > +tractGuidedSectionLib.inf > + > +############################################################### > ######## > +############################################################## > + > +# > +# Silicon Init Pei Library > +# > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc > + > +[LibraryClasses.IA32.SEC] > + > +[LibraryClasses.X64] > + # > + # DXE phase common > + # > + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf > + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf > + > +MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMem > oryAl > +locationLib.inf > + > +ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/Dxe > Ex > +tractGuidedSectionLib.inf > + > +# > +# Hsti > +# > + HstiLib|MdePkg/Library/DxeHstiLib/DxeHstiLib.inf > + > +############################################################### > ######## > +############################ > +# > +# Silicon Init Dxe Library > +# > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc > + > +[LibraryClasses.X64.PEIM] > + > +[LibraryClasses.X64.DXE_CORE] > + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf > + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > + > +[LibraryClasses.X64.DXE_SMM_DRIVER] > + > +SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesT > able > +Lib.inf > + > +MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMe > moryAllo > +cationLib.inf > + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf > + > +[LibraryClasses.X64.SMM_CORE] > + > +[LibraryClasses.X64.UEFI_DRIVER] > + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > + > +[LibraryClasses.X64.UEFI_APPLICATION] > + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf > + > +[Components.IA32] > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc > + > +[Components.X64] > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc > + > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc > b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc > new file mode 100644 > index 0000000000..b6d2058669 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc > @@ -0,0 +1,130 @@ > +## @file > +# Silicon build option configuration file. > +# > +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[BuildOptions] > +# Define Build Options both for EDK and EDKII drivers. > + > +# SA > +!if gSiPkgTokenSpaceGuid.PcdPttEnable == TRUE > + DEFINE PTT_BUILD_OPTION = -DPTT_FLAG=1 !else > + DEFINE PTT_BUILD_OPTION = > +!endif > + > +# > +# System Agent > +# > +!if gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE > + DEFINE DSC_SG_BUILD_OPTIONS = -DSG_SUPPORT=1 !else > + DEFINE DSC_SG_BUILD_OPTIONS = > +!endif > + > +!if gSiPkgTokenSpaceGuid.PcdBdatEnable == TRUE > + DEFINE BDAT_BUILD_OPTION = -DBDAT_SUPPORT=1 !else > + DEFINE BDAT_BUILD_OPTION = > +!endif > + > + DEFINE SLE_BUILD_OPTIONS = > +!if $(TARGET) == RELEASE > +!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE > + DEFINE DEBUG_BUILD_OPTIONS = > +!else > + # MDEPKG_NDEBUG is introduced for the intention > + # of size reduction when compiler optimization is disabled. If > +MDEPKG_NDEBUG is > + # defined, then debug and assert related macros wrapped by it are the NULL > implementations. > + DEFINE DEBUG_BUILD_OPTIONS = -DMDEPKG_NDEBUG !endif !else > + DEFINE DEBUG_BUILD_OPTIONS = > +!endif > + > +!if ($(TARGET) == RELEASE) AND > +(gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE) > + DEFINE RELEASE_CATALOG_BUILD_OPTIONS = -DRELEASE_CATALOG !else > + DEFINE RELEASE_CATALOG_BUILD_OPTIONS = !endif > + > +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE > + DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL- !else > + DEFINE OPTIMIZE_DISABLE_OPTIONS = > +!endif > + > + DEFINE HSLE_BUILD_OPTIONS = > + > +!if gSiPkgTokenSpaceGuid.PcdCflCpuEnable == TRUE > + DEFINE CPU_FLAGS = -DCPU_CFL > +!else > + DEFINE CPU_FLAGS = > +!endif > + > + > +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(BDAT_BUILD_OPTION) > +$(PTT_BUILD_OPTION) $(DEBUG_BUILD_OPTIONS) DEFINE > +DSC_SIPKG_FEATURE_BUILD_OPTIONS = > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > +$(DSC_SG_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(CPU_FLAGS) > +$(HSLE_BUILD_OPTIONS) $(RELEASE_CATALOG_BUILD_OPTIONS) > +$(DSC_TXT_BUILD_OPTIONS) > + > +!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == TRUE > + *_*_X64_GENFW_FLAGS = --keepexceptiontable !endif > + > +[BuildOptions.Common.EDKII] > + > +# > +# For IA32 Global Build Flag > +# > + *_*_IA32_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI > + *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + > +# > +# For IA32 Specific Build Flag > +# > +MSFT: *_*_IA32_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 > -DASF_PEI > +MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) > + > +# > +# For X64 Global Build Flag > +# > + *_*_X64_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=0x00010015 > + *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + > +# > +# For X64 Specific Build Flag > +# > +MSFT: *_*_X64_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 > +MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > + > +# > +# For Xcode Specific Build Flag > +# > +# Override assembly code build order > +*_XCODE5_*_*_BUILDRULEORDER = nasm S s > +# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of > +VA_START in undefined way *_XCODE5_*_CC_FLAGS = -Wno-varargs > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support > +page level protection of runtime modules > [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] > + MSFT: *_*_*_DLINK_FLAGS = /ALIGN:4096 > + GCC: *_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000 > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc > b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc > new file mode 100644 > index 0000000000..2df08c6d01 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc > @@ -0,0 +1,69 @@ > +## @file > +# Component description file for the Coffee Lake silicon package both PEI > and DXE libraries DSC file. > +# > +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +# > +# Set PCH generation according PCD. > +# The DEFINE will be used to select PCH library INF file corresponding > +to PCH generation # DEFINE PCH = Cnl > + > +# > +# Cpu > +# > + > CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatf > orm > + CpuPlatformLib|Lib/PeiDxeSmmCpuPlatformLib.inf > + > CpuMailboxLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/BaseCpuMailboxLib > Null > + CpuMailboxLib|/BaseCpuMailboxLibNull.inf > + > +# > +# Me > +# > + > +# > +# Pch > +# > + > PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPch > Cyc > + PchCycleDecodingLib|leDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf > + > PchGbeLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchGbeLib/Pe > iDxe > + PchGbeLib|SmmPchGbeLib.inf > + > PchInfoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchInfoLib/Pei > D > + PchInfoLib|xeSmmPchInfoLib$(PCH).inf > + > SataLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmSataLib/PeiDxeS > mmS > + SataLib|ataLib$(PCH).inf > + > PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcieRpLi > b/ > + PchPcieRpLib|PeiDxeSmmPchPcieRpLib.inf > + > PchPcrLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcrLib/PeiD > xe > + PchPcrLib|SmmPchPcrLib.inf > + > PmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSm > mPmc > + PmcLib|Lib.inf > + > + > PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSbiA > cce > + PchSbiAccessLib|ssLib/PeiDxeSmmPchSbiAccessLib.inf > + > GpioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmGpioLib/PeiDxeS > mmG > + GpioLib|pioLib.inf > +!if gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable == TRUE > + > PchSerialIoUartLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSe > ri > + PchSerialIoUartLib|alIoUartLib/PeiDxeSmmPchSerialIoUartLib.inf > +!else > + > PchSerialIoUartLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchSerialIoU > + PchSerialIoUartLib|artLibNull/BasePchSerialIoUartLibNull.inf > +!endif > + > PchSerialIoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSerialI > o > + PchSerialIoLib|Lib/PeiDxeSmmPchSerialIoLibCnl.inf > + > PchEspiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchEspiLib/Pe > iD > + PchEspiLib|xeSmmPchEspiLib.inf > + > PchWdtCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPch > WdtComm > + PchWdtCommonLib|onLib/PeiDxeSmmPchWdtCommonLib.inf > + > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib > /B > + ResetSystemLib|aseResetSystemLib.inf > + > SmbusLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseSmbusLib/BaseSmbus > Lib. > + SmbusLib|inf > + > BiosLockLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmBiosLockLib/ > Pe > + BiosLockLib|iDxeSmmBiosLockLib.inf > + #private > + > PchPciExpressHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/Pei > + > PchPciExpressHelpersLib|DxeSmmPchPciExpressHelpersLib/PeiDxeSmmPchPc > iE > + PchPciExpressHelpersLib|xpressHelpersLib.inf > + > PchInitCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeS > mmP > + PchInitCommonLib|chInitCommonLib/PeiDxeSmmPchInitCommonLib.inf > + > PchSpiCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BasePchS > piC > + PchSpiCommonLib|ommonLib/BasePchSpiCommonLib.inf > + > GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmG > pi > + GpioPrivateLib|oPrivateLib/PeiDxeSmmGpioPrivateLibCnl.inf > + > PchPsfPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmm > P > + PchPsfPrivateLib|chPsfPrivateLib/PeiDxeSmmPchPsfPrivateLib$(PCH).inf > + > PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmP > mcP > + PmcPrivateLib|rivateLib/PeiDxeSmmPmcPrivateLibCnl.inf > + > PmcPrivateLibWithS3|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxe > S > + > PmcPrivateLibWithS3|mmPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf > + > PchDmiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchD > miLi > + PchDmiLib|b/PeiDxeSmmPchDmiLib.inf > + > PchDmiWithS3Lib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSm > mPc > + PchDmiWithS3Lib|hDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf > + > SiScheduleResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BaseSiSc > + SiScheduleResetLib|heduleResetLib/BaseSiScheduleResetLib.inf > + > +# > +# SA > +# > + > SaPlatformLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiDxeSmmS > aPl > + SaPlatformLib|atformLib/PeiDxeSmmSaPlatformLib.inf > + > +# > +# Memory > +# > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc > b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc > new file mode 100644 > index 0000000000..07677ece1a > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc > @@ -0,0 +1,33 @@ > +## @file > +# Component description file for the Coffee Lake silicon package DXE > drivers. > +# > +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +# > +# Common > +# > + > +# > +# Pch > +# > + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf > + $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf > + > + $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf > + > + > $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.in > f > + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf > + > +# > +# SystemAgent > +# > + $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf > + > +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE > + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf > + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf > +!endif > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc > b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc > new file mode 100644 > index 0000000000..214de06d58 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc > @@ -0,0 +1,37 @@ > +## @file > +# Component description file for the Coffee Lake silicon package DXE > libraries. > +# > +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +# > +# Silicon Init Dxe Library > +# > + > +# > +# Common > +# > +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE > + > AslUpdateLib|$(PLATFORM_SI_PACKAGE)/Library/DxeAslUpdateLib/DxeAslU > pda > + AslUpdateLib|teLib.inf > +!else > + > AslUpdateLib|$(PLATFORM_SI_PACKAGE)/Library/DxeAslUpdateLibNull/DxeA > sl > + AslUpdateLib|UpdateLibNull.inf > +!endif > + > SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B > + SiConfigBlockLib|aseSiConfigBlockLib.inf > + > +# > +# Pch > +# > + > PchHdaLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/DxePchHdaLib/Dx > eP > + PchHdaLib|chHdaLib.inf > + > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeResetSystemLib/ > Dx > + ResetSystemLib|eResetSystemLib.inf > + > DxePchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxePchPolicyLib/Dxe > + DxePchPolicyLib|PchPolicyLib.inf > + > GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BaseGpioHel > p > + GpioHelpersLib|ersLibNull/BaseGpioHelpersLibNull.inf > + > GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/DxeGpio > Na > + GpioNameBufferLib|meBufferLib/DxeGpioNameBufferLib.inf > + > SmmPchPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/SmmPchP > riv > + SmmPchPrivateLib|ateLib/SmmPchPrivateLib.inf > + > +# > +# SystemAgent > +# > + > DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaPolicy > L > + DxeSaPolicyLib|ib/DxeSaPolicyLib.inf > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc > b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc > new file mode 100644 > index 0000000000..f30c7e0ae1 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc > @@ -0,0 +1,21 @@ > +## @file > +# Component description file for theCoffee Lake silicon package PEI drivers. > +# > +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +# > +# Common > +# > + > +# > +# SystemAgent > +# > + > +# > +# Cpu > +# > + > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc > b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc > new file mode 100644 > index 0000000000..6e244a6ded > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc > @@ -0,0 +1,44 @@ > +## @file > +# Component description file for the Coffee Lake silicon package PEI > libraries. > +# > +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> # # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +# > +# Silicon Init Pei Library > +# > + SiPolicyLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiPolicyLib/PeiSiPolicyL > + SiPolicyLib|ib.inf > + > SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B > + SiConfigBlockLib|aseSiConfigBlockLib.inf > + StallPpiLib|$(PLATFORM_SI_PACKAGE)/Library/PeiInstallStallPpiLib/PeiSt > + StallPpiLib|allPpiLib.inf > + > +# > +# Pch > +# > + > PchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchPolicyLib/PeiPch > + PchPolicyLib|PolicyLibCnl.inf > +!if gSiPkgTokenSpaceGuid.PcdOcWdtEnable == TRUE > + > OcWdtLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiOcWdtLib/PeiOcWdtLib > .in > + OcWdtLib|f > +!else > + > OcWdtLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiOcWdtLibNull/PeiOcWd > tLi > + OcWdtLib|bNull.inf > +!endif > + > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiResetSystemLib/P > e > + ResetSystemLib|iResetSystemLib.inf > + > PchResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchResetLib/PeiPchR > e > + PchResetLib|setLib.inf > + SpiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiSpiLib/PeiSpiLib.inf > + > GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiGpioHelp > e > + GpioHelpersLib|rsLib/PeiGpioHelpersLib.inf > + > GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiGpio > Na > + GpioNameBufferLib|meBufferLib/PeiGpioNameBufferLib.inf > + > +# > +# Me > +# > + > PeiMePolicyLib|$(PLATFORM_SI_PACKAGE)/Me/Library/PeiMePolicyLib/PeiM > eP > + PeiMePolicyLib|olicyLib.inf > + > +# > +# SA > +# > + > +PeiSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiSaPolicy > Li > +b/PeiSaPolicyLib.inf > +# > +# Cpu > +# > + > CpuPolicyLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiCpuPolicyLib/PeiCp > u > + CpuPolicyLib|PolicyLib.inf > -- > 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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