Reviewed-by: Chasel Chiu <chasel.c...@intel.com>
> -----Original Message----- > From: Kubacki, Michael A > Sent: Saturday, August 17, 2019 8:15 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaga...@intel.com>; Chiu, Chasel > <chasel.c...@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desim...@intel.com>; Gao, Liming <liming....@intel.com>; > Kinney, Michael D <michael.d.kin...@intel.com>; Sinha, Ankit > <ankit.si...@intel.com> > Subject: [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add > Include headers > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082 > > Adds header files common to ME modules. > > Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> > Cc: Chasel Chiu <chasel.c...@intel.com> > Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> > Cc: Liming Gao <liming....@intel.com> > Cc: Michael D Kinney <michael.d.kin...@intel.com> > Cc: Ankit Sinha <ankit.si...@intel.com> > Signed-off-by: Michael Kubacki <michael.a.kuba...@intel.com> > --- > Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h | > 124 ++++++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyLib.h | > 59 +++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyLib.h | > 87 ++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h | 172 > ++++++++++++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h | 17 > ++ > Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h | 19 > +++ > Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h | > 41 +++++ > 7 files changed, 519 insertions(+) > > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h > new file mode 100644 > index 0000000000..102fb43bd1 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiCon > +++ fig.h > @@ -0,0 +1,124 @@ > +/** @file > + ME config block for PEI phase > + > + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _ME_PEI_CONFIG_H_ > +#define _ME_PEI_CONFIG_H_ > + > +#include <ConfigBlock.h> > + > +#define ME_PEI_PREMEM_CONFIG_REVISION 2 extern EFI_GUID > +gMePeiPreMemConfigGuid; > + > +#ifndef PLATFORM_POR > +#define PLATFORM_POR 0 > +#endif > +#ifndef FORCE_ENABLE > +#define FORCE_ENABLE 1 > +#endif > +#ifndef FORCE_DISABLE > +#define FORCE_DISABLE 2 > +#endif > + > +#pragma pack (push,1) > + > +/** > + ME Pei Pre-Memory Configuration Structure. > + > + <b>Revision 1:</b> > + - Initial version. > + <b>Revision 2</b>: > + - Change DidInitStat bit width. > +**/ > +typedef struct { > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header > + UINT32 HeciTimeouts : 1; ///< 0: Disable; <b>1: > Enable</b> > - HECI Send/Receive Timeouts. > + /** > + <b>(Test)</b> > + <b>0: Disabled</b> > + 1: ME DID init stat 0 - Success > + 2: ME DID init stat 1 - No Memory in Channels > + 3: ME DID init stat 2 - Memory Init Error > + **/ > + UINT32 DidInitStat : 2; > + /** > + <b>(Test)</b> > + <b>0: Set to 0 to enable polling for CPU replacement</b> > + 1: Set to 1 will disable polling for CPU replacement > + **/ > + UINT32 DisableCpuReplacedPolling : 1; > + UINT32 SendDidMsg : 1; ///< <b>(Test)</b> 0: > Disable; > <b>1: Enable</b> - Enable/Disable to send DID message. > + /** > + <b>(Test)</b> > + <b>0: Set to 0 to enable retry mechanism for HECI APIs</b> > + 1: Set to 1 will disable retry mechanism for HECI APIs > + **/ > + UINT32 DisableHeciRetry : 1; > + /** > + <b>(Test)</b> > + <b>0: ME BIOS will check each messages before sending</b> > + 1: ME BIOS always sends messages without checking > + **/ > + UINT32 DisableMessageCheck : 1; > + /** > + <b>(Test)</b> > + The SkipMbpHob policy determines whether ME BIOS Payload data will be > requested during boot > + in a MBP message. If set to 1, BIOS will send the MBP message with > SkipMbp flag > + set causing CSME to respond with MKHI header only and no MBP data > + <b>0: ME BIOS will keep MBP and create HOB for MBP data</b> > + 1: ME BIOS will skip MBP data > + **/ > + UINT32 SkipMbpHob : 1; > + UINT32 HeciCommunication2 : 1; ///< <b>(Test)</b> <b>0: > Disable</b>; 1: Enable - Enable/Disable HECI2. > + UINT32 KtDeviceEnable : 1; ///< <b>(Test)</b> 0: > Disable; > <b>1: Enable</b> - Enable/Disable Kt Device. > + UINT32 RsvdBits : 22; ///< Reserved for future use > & > Config block alignment > + UINT32 Heci1BarAddress; ///< HECI1 BAR address. > + UINT32 Heci2BarAddress; ///< HECI2 BAR address. > + UINT32 Heci3BarAddress; ///< HECI3 BAR address. > +} ME_PEI_PREMEM_CONFIG; > +#pragma pack (pop) > + > + > +#define ME_PEI_CONFIG_REVISION 2 > +extern EFI_GUID gMePeiConfigGuid; > + > +#pragma pack (push,1) > + > +/** > + ME Pei Post-Memory Configuration Structure. > + > + <b>Revision 1:</b> > + - Initial version. > + <b>Revision 2</b>: > + - Add MctpBroadcastCycle test setting. > +**/ > +typedef struct { > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header > + > + UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send in > PEI; > <b>2: Send in DXE</b> - Send EOP at specific phase. > + /** > + HECI3 state from Mbp for reference in S3 path only > + <b>0: Disabled</b>; 1: Enabled > + **/ > + UINT32 Heci3Enabled : 1; > + UINT32 DisableD0I3SettingForHeci : 1; ///< <b>(Test)</b> <b>0: > Disable</b>; 1: Enable - Enable/Disable D0i3 for HECI. > + /** > + Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send > MeUnconfigOnRtcClearDisable Msg with parameter 0. > + It will cause ME to unconfig if RTC is cleared. > + - 0: Disable > + - <b>1: Enable</b> > + - 2: Cmos is clear, status unkonwn > + - 3: Reserved > + **/ > + UINT32 MeUnconfigOnRtcClear : 2; > + UINT32 MctpBroadcastCycle : 1; ///< <b>(Test)</b> <b>0: > Disable</b>; 1: Enable - Program registers for MCTP Cycle. > + UINT32 RsvdBits : 25; ///< Reserved for future > use & > Config block alignment > +} ME_PEI_CONFIG; > + > +#pragma pack (pop) > + > +#endif // _ME_PEI_CONFIG_H_ > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyLib.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyLib.h > new file mode 100644 > index 0000000000..46f7f86021 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyL > +++ ib.h > @@ -0,0 +1,59 @@ > +/** @file > + Prototype of the DxeMePolicyLib library. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _DXE_ME_POLICY_LIB_H_ > +#define _DXE_ME_POLICY_LIB_H_ > + > +#include <Protocol/MePolicy.h> > + > +/** > + This function prints the ME DXE phase policy. > + > + @param[in] DxeMePolicy - ME DXE Policy protocol **/ VOID > +MePrintPolicyProtocol ( > + IN ME_POLICY_PROTOCOL *DxeMePolicy > + ); > + > +/** > + MeCreatePolicyDefaults creates the default setting of ME Policy. > + It allocates and zero out buffer, and fills in the Intel default settings. > + > + @param[in, out] DxeMePolicy The pointer to get ME Policy protocol > instance > + > + @retval EFI_SUCCESS The policy default is initialized. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer > + > +**/ > +EFI_STATUS > +EFIAPI > +MeCreatePolicyDefaults ( > + IN OUT ME_POLICY_PROTOCOL **DxeMePolicy > + ); > + > +/** > + MeInstallPolicyProtocol installs ME Policy. > + While installed, RC assumes the Policy is ready and finalized. So > +please update and override > + any setting before calling this function. > + > + @param[in] ImageHandle Image handle of this driver. > + @param[in] DxeMePolicy The pointer to ME Policy Protocol > instance > + > + @retval EFI_SUCCESS The policy is installed. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer > + > +**/ > +EFI_STATUS > +EFIAPI > +MeInstallPolicyProtocol ( > + IN EFI_HANDLE ImageHandle, > + IN ME_POLICY_PROTOCOL *DxeMePolicy > + ); > + > +#endif // _DXE_ME_POLICY_LIB_H_ > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyLib.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyLib.h > new file mode 100644 > index 0000000000..5db4714346 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyL > +++ ib.h > @@ -0,0 +1,87 @@ > +/** @file > + Prototype of the MePolicyLibPei library. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _PEI_ME_POLICY_LIB_H_ > +#define _PEI_ME_POLICY_LIB_H_ > + > +#include <Ppi/SiPolicy.h> > +#include <Library/ConfigBlockLib.h> > + > +/** > + This function prints the PEI phase PreMem policy. > + > + @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI > instance > +**/ > +VOID > +EFIAPI > +MePrintPolicyPpiPreMem ( > + IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi > + ); > + > +/** > + This function prints the PEI phase policy. > + > + @param[in] SiPolicyPpi The RC Policy PPI instance > +**/ > +VOID > +EFIAPI > +MePrintPolicyPpi ( > + IN SI_POLICY_PPI *SiPolicyPpi > + ); > + > +/** > + Get Me config block table total size. > + > + @retval Size of Me config block table > +**/ > +UINT16 > +EFIAPI > +MeGetConfigBlockTotalSize ( > + VOID > + ); > + > +/** > + Get ME config block table total size. > + > + @retval Size of ME config block table > +**/ > +UINT16 > +EFIAPI > +MeGetConfigBlockTotalSizePreMem ( > + VOID > + ); > + > +/** > + MeAddConfigBlocksPreMem add all ME config blocks. > + > + @param[in] ConfigBlockTableAddress The pointer to add ME config > blocks > + > + @retval EFI_SUCCESS The policy default is initialized. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer > +**/ > +EFI_STATUS > +EFIAPI > +MeAddConfigBlocksPreMem ( > + IN VOID *ConfigBlockTableAddress > + ); > + > +/** > + MeAddConfigBlocks add all ME config blocks. > + > + @param[in] ConfigBlockTableAddress The pointer to add ME config > blocks > + > + @retval EFI_SUCCESS The policy default is initialized. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer > +**/ > +EFI_STATUS > +EFIAPI > +MeAddConfigBlocks ( > + IN VOID *ConfigBlockTableAddress > + ); > + > +#endif // _PEI_ME_POLICY_LIB_H_ > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h > new file mode 100644 > index 0000000000..f29f9bc8bd > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h > @@ -0,0 +1,172 @@ > +/** @file > + Chipset definition for ME Devices. > + > + Conventions: > + > + - Prefixes: > + - Definitions beginning with "R_" are registers > + - Definitions beginning with "B_" are bits within registers > + - Definitions beginning with "V_" are meaningful values of bits within > the > registers > + - Definitions beginning with "S_" are register sizes > + - Definitions beginning with "N_" are the bit position > + - Registers / bits that are different between PCH generations are denoted > by > + "_ME_[generation_name]_" in register/bit names. > + - Registers / bits that are specific to PCH-H denoted by "PCH_H_" in > register/bit names. > + Registers / bits that are specific to PCH-LP denoted by "PCH_LP_" in > register/bit names. > + e.g., "_ME_PCH_H_", "_ME_PCH_LP_" > + Registers / bits names without _PCH_H_ or _PCH_LP_ apply for both H and > LP. > + - Registers / bits that are different between SKUs are denoted by > "_[SKU_name]" > + at the end of the register/bit names > + - Registers / bits of new devices introduced in a PCH generation will be > just > named > + as "_ME_" without [generation_name] inserted. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _ME_CHIPSET_H_ > +#define _ME_CHIPSET_H_ > + > +#define ME_SEGMENT 0 > +#define ME_BUS 0 > +#define ME_DEVICE_NUMBER 22 > +#define HECI_MIN_FUNC 0 > +#define HECI_MAX_FUNC 5 > + > +#define HECI_FUNCTION_NUMBER 0x00 > +#define HECI2_FUNCTION_NUMBER 0x01 > +#define IDER_FUNCTION_NUMBER 0x02 > +#define SOL_FUNCTION_NUMBER 0x03 > +#define HECI3_FUNCTION_NUMBER 0x04 > +#define HECI4_FUNCTION_NUMBER 0x05 > + > +#define IDER_BUS_NUMBER ME_BUS > +#define IDER_DEVICE_NUMBER ME_DEVICE_NUMBER > +#define SOL_BUS_NUMBER ME_BUS > +#define SOL_DEVICE_NUMBER ME_DEVICE_NUMBER > + > + /// > +/// Convert to HECI# defined in BWG from Fun# /// #define > +HECI_NAME_MAP(a) ((a < 2) ? (a + 1) : (a - 1)) > + > +/// > +/// ME-related Chipset Definition > +/// > +#define HeciEnable() MeDeviceControl (HECI1, Enabled); > +#define Heci2Enable() MeDeviceControl (HECI2, Enabled); > +#define Heci3Enable() MeDeviceControl (HECI3, Enabled); > +#define Heci4Enable() MeDeviceControl (HECI4, Enabled); > +#define IderEnable() MeDeviceControl (IDER, Enabled); > +#define SolEnable() MeDeviceControl (SOL, Enabled); > + > +#define HeciDisable() MeDeviceControl (HECI1, Disabled); > +#define Heci2Disable() MeDeviceControl (HECI2, Disabled); #define > +Heci3Disable() MeDeviceControl (HECI3, Disabled); > +#define IderDisable() MeDeviceControl (IDER, Disabled); > +#define SolDisable() MeDeviceControl (SOL, Disabled); > + > +#define DisableAllMeDevices() \ > + HeciDisable (); \ > + Heci2Disable (); \ > + Heci3Disable (); \ > + IderDisable (); \ > + SolDisable (); > + > +/// > +/// HECI Device Id Definitions > +/// > + #define IS_PCH_H_HECI_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_H_HECI_DEVICE_ID) \ > + ) > + > + #define IS_PCH_LP_HECI_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_LP_HECI_DEVICE_ID) \ > + ) > + > + #define IS_HECI_DEVICE_ID(DeviceId) \ > + ( \ > + IS_PCH_H_HECI_DEVICE_ID(DeviceId) || \ > + IS_PCH_LP_HECI_DEVICE_ID(DeviceId) \ > + ) > + > +/// > +/// HECI2 Device Id Definitions > +/// > +#define IS_PCH_H_HECI2_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_H_HECI2_DEVICE_ID) \ > + ) > + > +#define IS_PCH_LP_HECI2_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_LP_HECI2_DEVICE_ID) \ > + ) > + > +#define IS_HECI2_DEVICE_ID(DeviceId) \ > + ( \ > + IS_PCH_H_HECI2_DEVICE_ID(DeviceId) || \ > + IS_PCH_LP_HECI2_DEVICE_ID(DeviceId) \ > + ) > + > +/// > +/// HECI3 Device Id Definitions > +/// > +#define IS_PCH_H_HECI3_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_H_HECI3_DEVICE_ID) \ > + ) > + > +#define IS_PCH_LP_HECI3_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_LP_HECI3_DEVICE_ID) \ > + ) > + > +#define IS_HECI3_DEVICE_ID(DeviceId) \ > + ( \ > + IS_PCH_H_HECI3_DEVICE_ID(DeviceId) || \ > + IS_PCH_LP_HECI3_DEVICE_ID(DeviceId) \ > + ) > + > +/// > +/// HECI4 Device Id Definitions > +/// > +#define IS_PCH_H_HECI4_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_H_HECI4_DEVICE_ID) \ > + ) > + > +#define IS_PCH_LP_HECI4_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_LP_HECI4_DEVICE_ID) \ > + ) > + > +#define IS_HECI4_DEVICE_ID(DeviceId) \ > + ( \ > + IS_PCH_H_HECI4_DEVICE_ID(DeviceId) || \ > + IS_PCH_LP_HECI4_DEVICE_ID(DeviceId) \ > + ) > + > +/// > +/// SoL Device Id Definitions > +/// > +#define IS_PCH_H_SOL_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_H_SOL_DEVICE_ID) \ > + ) > + > +#define IS_PCH_LP_SOL_DEVICE_ID(DeviceId) \ > + ( \ > + (DeviceId == V_ME_PCH_LP_SOL_DEVICE_ID) \ > + ) > + > +#define IS_PCH_SOL_DEVICE_ID(DeviceId) \ > + ( \ > + IS_PCH_H_SOL_DEVICE_ID(DeviceId) || \ > + IS_PCH_LP_SOL_DEVICE_ID(DeviceId) \ > + ) > + > +#endif > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h > new file mode 100644 > index 0000000000..a24973ce32 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h > @@ -0,0 +1,17 @@ > +/** @file > + This file contains definitions of ME Policy HOB. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _ME_POLICY_HOB_H_ > +#define _ME_POLICY_HOB_H_ > + > +#include <MePolicyCommon.h> > + > +extern EFI_GUID gMePolicyHobGuid; > +extern EFI_GUID gMePreMemPolicyHobGuid; > + > +#endif // _ME_POLICY_HOB_H_ > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h > new file mode 100644 > index 0000000000..2d8ef1cf7a > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h > @@ -0,0 +1,19 @@ > +/** @file > + MKHI Messages > + > + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _MKHI_MSGS_H > +#define _MKHI_MSGS_H > + > +/// > +/// End of Post > +/// > +#define EOP_DISABLED 0 > +#define EOP_SEND_IN_PEI 1 > +#define EOP_SEND_IN_DXE 2 > + > +#endif // _MKHI_MSGS_H > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h > new file mode 100644 > index 0000000000..518041cb58 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h > @@ -0,0 +1,41 @@ > +/** @file > + Interface definition details between ME and platform drivers during DXE > phase. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _ME_POLICY_H_ > +#define _ME_POLICY_H_ > + > +#include <ConfigBlock.h> > + > +/** > + ME Policy Protocol. > + All ME Policy Protocol change history listed here. > + > +**/ > +#define ME_POLICY_PROTOCOL_REVISION 1 > + > +extern EFI_GUID gDxeMePolicyGuid; > + > +#pragma pack (push,1) > + > +/** > + ME policy provided by platform for DXE phase > + This protocol provides an interface to get Intel ME Configuration > +information > + > + <b>Revision 1</b>: > + - Initial version. > +**/ > +typedef struct _ME_POLICY_PROTOCOL { > + CONFIG_BLOCK_TABLE_HEADER TableHeader; > +/* > + Individual Config Block Structures are added here in memory as part > +of AddConfigBlock() */ } ME_POLICY_PROTOCOL; > + > +#pragma pack (pop) > + > +#endif // _ME_POLICY_H_ > -- > 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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