REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
PcdFsp*BaseAddress now will be updated in FDF basing on flash map. DSC will only define types of those PCDs and always having 0 as default. Test: interanl platform booted with this patch. Cc: Michael Kubacki <michael.a.kuba...@intel.com> Cc: Ankit Sinha <ankit.si...@intel.com> Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> Cc: Liming Gao <liming....@intel.com> Signed-off-by: Chasel Chiu <chasel.c...@intel.com> --- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 3 +++ Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 12 +++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf index da498ad379..c425e4b280 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf @@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize ################################################################################ diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc index c6bce19856..83cbd18557 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc @@ -109,8 +109,11 @@ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 !endif - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processorss @@ -201,7 +204,10 @@ !endif [PcdsDynamicDefault] - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000 + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 # Platform will pre-allocate UPD buffer and pass it to FspWrapper # Those dummy address will be patched before FspWrapper executing gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#44511): https://edk2.groups.io/g/devel/message/44511 Mute This Topic: https://groups.io/mt/32640910/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
