The primary SPI controller on SynQuacer is reserved for the NOR
flash, and is not exposed to the OS. The second SPI controller is
wired to the low speed 96boards connector on DeveloperBox, and so
in order to use it, we must describe it to the OS (like we already
do in the device tree). So add the description to the DSDT as well.
Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 19
+++++++++++++++++++
Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++
2 files changed, 23 insertions(+)
diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
index c8d8120d262a..f6ff3988aa91 100644
--- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
+++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
@@ -251,5 +251,24 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI",
"SYNQUACR",
Device (PWRB) {
Name (_HID, "PNP0C0C")
}
+
+ Device (SPI0) {
+ Name (_HID, "SCX0004")
+ Name (_UID, Zero)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, SYNQUACER_SPI1_BASE, SYNQUACER_SPI1_SIZE)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 192, 193,
194 }
+ })
+
+ Name (_DSD, Package () // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package (2) { "socionext,ihclk-rate", 125000000 },
+ Package (2) { "socionext,use-rtm", 1 },
+ Package (2) { "socionext,set-aces", 1 },
+ }
+ })
+ }
} // Scope (_SB)
}
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
index deb9c81e82e6..29c5f73f2057 100644
--- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
@@ -78,4 +78,8 @@
#define SYNQUACER_UART1_BASE 0x51040000
#define SYNQUACER_UART1_SIZE SIZE_4KB
+// SPI controller #1
+#define SYNQUACER_SPI1_BASE 0x54810000
+#define SYNQUACER_SPI1_SIZE SIZE_4KB
+
#endif
--
2.20.1
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