Extend MADT GICC table flags with PERFORMANCE_INTERRUPT_MODEL,
which is responsible for configuring interrupt type in the OS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
b/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
index 3dae5d3..7ab927d 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
@@ -35,6 +35,8 @@
#define PMU_INTERRUPT_CPU2 132
#define PMU_INTERRUPT_CPU3 133
+#define PMU_INTERRUPT_FLAG EFI_ACPI_6_0_GIC_ENABLED |
EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL
+
#pragma pack(push, 1)
typedef struct {
EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
@@ -57,7 +59,7 @@ ACPI_6_0_MADT_STRUCTURE Madt = {
EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId
0x000, // AcpiCpuUid
0x000, // Mpidr
- EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_FLAG, // Flags
PMU_INTERRUPT_CPU0, // PmuIrq
GICC_BASE, // GicBase
GICV_BASE, // GicVBase
@@ -69,7 +71,7 @@ ACPI_6_0_MADT_STRUCTURE Madt = {
EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId
0x001, // AcpiCpuUid
0x001, // Mpidr
- EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_FLAG, // Flags
PMU_INTERRUPT_CPU1, // PmuIrq
GICC_BASE, // GicBase
GICV_BASE, // GicVBase
@@ -81,7 +83,7 @@ ACPI_6_0_MADT_STRUCTURE Madt = {
EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId
0x100, // AcpiCpuUid
0x100, // Mpidr
- EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_FLAG, // Flags
PMU_INTERRUPT_CPU2, // PmuIrq
GICC_BASE, // GicBase
GICV_BASE, // GicVBase
@@ -93,7 +95,7 @@ ACPI_6_0_MADT_STRUCTURE Madt = {
EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId
0x101, // AcpiCpuUid
0x101, // Mpidr
- EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_FLAG, // Flags
PMU_INTERRUPT_CPU3, // PmuIrq
GICC_BASE, // GicBase
GICV_BASE, // GicVBase
--
2.7.4
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