Re: [apache/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA #3009 (#3010)

[lyxcliang]

use 
https://github.com/apache/tvm-vta/tree/87ce9acfae550d1a487746e9d06c2e250076e54c/apps/tsim_example
 was OK. but when run "python3 tests/python/verilog_accel.py", it reported: 
libhw.so: undefined symbol : VTASimDPI
![image](https://user-images.githubusercontent.com/87418712/149775311-18afbfec-ea0d-49cb-832d-ce3519e11d54.png)

the generated code is:

why?

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