thanks for the writeup @wrongtest! a couple points I am more curious about:
[quote="wrongtest, post:1, topic:11807"] Our tir schedule phase would rewrite tensor layouts to fit hardware features, so we modify the compile engine to give a chance of compatible updates at relay level. [/quote] could you say more here? is this a Relay-level thing or a TIR thing? presuming you've implemented this as a pass, how do you plan to ensure that the Relay-level pass makes the same scheduling decision as the TIR pass? [quote="wrongtest, post:1, topic:11807"] They are available after upstreaming. Also, we are more than glad to provide Docker environments for anyone interested in our hardware. [/quote] it seems like this could either be integrated into `ci-cpu` or as a separate `ci-` image, so long as the binaries are publicly available. do you have an estimate of the size of the docker image? also, just for my curiosity, would you be able to share a rough timeline of when you'd like to land this? --- [Visit Topic](https://discuss.tvm.apache.org/t/introducing-ty-nnp-backend-with-end2end-tensorir-integration/11807/3) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/875e6a660e797a10a1045e3871fee9db60c96dc931d43970509d90078f87fe8b).
