Thanks @MeeraN7 for the RFC. SVE is certainly an interesting topic that can be covered in different ways.
It would be very helpful to also show examples of the code along the transformations, so we can have a better understanding the possible design tradeoffs. Specifically: - The TIR before SVE vectorization - The TIR after SVE vectorization right before LLVM codegen - The corresponding lowered llvm intrinsics -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/apache/tvm-rfcs/pull/18#issuecomment-893549153
