Should any of these be mentioned in the NuttX website, maybe in a new "Who's Using NuttX" section?
On Mon, Jun 23, 2025 at 1:27 AM Alin Jerpelea <jerpe...@gmail.com> wrote: > Hi Pavel, > > thanks for sharing the information > > Best regards > Alin > > > On Sun, 22 Jun 2025, 09:48 Pavel Pisa, <ppisa4li...@pikron.com> wrote: > > > Hello everybody, > > > > [resent from another account to pass onto NuttX devel list] > > > > I want to inform you about three successfully defended theses > > theses at https://fel.cvut.cz/ which I have supervised this year > > as well as bout two supervised by my colleague from https://fit.cvut.cz/ > > which I have mentioned in the followup discussion after prof. David > > Harris new book introduction. > > > > All are embedded related and three use NuttX directly. > > Jan Medek's one ven includes his RTOSes comparison > > where NuttX doees stand well and has been chosen > > for porting to own FPGA designs. > > > > The link to Fediverse notice > > > > https://social.kernel.org/notice/AvMlkhuOLOKYrgeEhU > > > > Inlined Mark Down source to provide access the URLs > > > > Summer 2025 #cvut [defended theses] > > (https://gitlab.fel.cvut.cz/otrees/org/-/wikis/theses-defend) by > [OTREES] > > (https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home)/my students: > > - Matyáš Bobek, [FlexCAN Controller Emulation for QEMU] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/122654/F3-BP-2025-Bobek-Matyas-BP_Bobek_FlexCAN_final_4.pdf > ), > > > > #qemu #canbus ([git](https://gitlab.fel.cvut.cz/bobekmat/qemu-flexcan)), > > I > > hope for mainlining soon, my thanks to > > @marckleinebu...@fosstodon.org for [review] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/122654/F3-BP-2025-posudek-Kleine_Budde_Marc.pdf > > ) > > - Albert Bezděk, [Stereo Camera FPGA Interface and Processing for Zynq > > Based > > Systems] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/122779/F3-BP-2025-Bezdek-Albert-mzapo_cameras_report%20 > > (7).pdf), with initial rectification and disparity in #XilinX #Zynq #FPGA > > ([git](https://gitlab.fel.cvut.cz/otrees/fpga/mzapo-cameras)), thank to > > Martin Meloun for [review] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/122779/F3-BP-2025-posudek-Meloun_Martin.pdf > > ) > > - Michal Matiáš, [NuttX RTOS Driver for Single Unshielded Twisted Pair > > Communication] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/123231/F3-BP-2025-Matias-Michal-bp.pdf > ), > > > > working with ncv7410 and ESP32-C6 for now ([nuttx] > > (https://github.com/matiamic/nuttx/tree/ncv7410-wip), [apps] > > (https://github.com/matiamic/nuttx-apps/tree/ncv7410-wip) git), > continues > > by > > #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S > > for > > mainline #NuttX support after summer, thanks to @cyn...@mastodonczech.cz > > for > > [review] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/123231/F3-BP-2025-posudek-Koci_Karel.pdf > > ) > > > > See the last OTREES [theses list] > > (https://gitlab.fel.cvut.cz/otrees/org/-/wikis/theses-defend) for link > to > > repositories and more > > > > Another related theses from #cvut Faculty of Information Technologies > > mentored > > by Michal Štepanovský to mention: > > - Jan Medek, [Implementation of RISC-V soft-core processor on FPGA > board > > with real-time operating system support] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/123186/F8-DP-2025-Medek-Jan-thesis.pdf > ), > > > > port ([git] > > ( > > > https://github.com/medexs/nuttx/tree/ibex-demo-system-on-basys3-and-nexys-video > )) > > > > of #NuttX to the own setup of [Ibex] > > ( > https://github.com/medexs/ibex-demo-system/tree/read-spi-rx-data-support) > > > > #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even > #NuttX, > > #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor > > clarifications in my [review] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/123186/F8-DP-2025-posudek-Pisa_Pavel.pdf > ), > > > > out of the text documentation, the student ported NuttX even to the CPU > > system prepared in frame of the next thesis > > - Ondřej Golasowski, [RISC-V open-source microarchitecture analysis and > > optimization] > > ( > > > https://dspace.cvut.cz/bitstream/handle/10467/123187/F8-DP-2025-Golasowski-Ondrej-thesis.pdf > ), > > > > the [VESP-BETA](https://github.com/HoneyGol-Microsystems/vesp-beta) > > single-cycle RV32IMZicsr #riscv design for basic #comparch education with > > #FPGA labs > > > > Best wishes, > > > > Pavel > > > > Pavel Pisa > > > > phone: +420 603531357 > > e-mail: p...@cmp.felk.cvut.cz > > Department of Control Engineering FEE CVUT > > Karlovo namesti 13, 121 35, Prague 2 > > university: http://control.fel.cvut.cz/ > > personal: http://cmp.felk.cvut.cz/~pisa > > company: https://pikron.com/ PiKRON s.r.o. > > Kankovskeho 1235, 182 00 Praha 8, Czech Republic > > projects: https://www.openhub.net/accounts/ppisa > > social: https://social.kernel.org/ppisa > > CAN related:http://canbus.pages.fel.cvut.cz/ > > RISC-V education: https://comparch.edu.cvut.cz/ > > Open Technologies Research Education and Exchange Services > > https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home > > >
