RISC-V Debug and Semihosting Specifications were ratified today, not yet published documents versions 1.0 but they are coming soon after years of work :-)
---------- Forwarded message --------- From: Jeff Scheel via lists.riscv.org Date: Thu, Feb 20, 2025 at 9:55 PM Subject: [RISC-V tech-announce] RISC-V Ratifies the Debug 1.0, Load/Store Pair for RV32, Semihosting, and Server SOC Specifications All, The following specifications were ratified in the RISC-V Board of Directors meeting on February 20, 2025: 1. RISC-V Debug Specification version 1.0 (extensions Sdext & Sdtrig as well as non-ISA support) (PDF, Jira) led by Tim Newsome and Paul Donahue under governance of the SOC Infrastructure Horizontal Committee and the Debug Task Group 2. Load/Store Pair for RV32 specification version 1.0 (Fast Track extensions Zilsd & Zclsd) (PDF, Jira) led by Christian Herber under governance of the Unprivileged ISA Committee 3. RISC-V Semihosting specification version 1.0 (Fast Track non-ISA) (PDF, Jira) led by Anup Patel under guidance of the Privileged Software Horizontal Committee 4. RISC-V Server SoC Specification version 1.0 (PDF, Jira) (non-ISA) led by Ved Shanbhogue under the guidance of the SOC Infrastructure Horizontal Committee and the Server SOC Task Group These are the first 4 ratifications of the 2025 year. For more information, see the Technical Specifications (Non-ISA section) and the Ratified Extensions wiki pages. Note: the documents are in the process of being updated to indicate the new status and will be posted at the linked locations when available. Please join us in thanking the authors and all who contributed to these specifications. - RISC-V International -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
