Hi,
A devboard with no jtag makes no sense for me! When you have a hw
revision with both the esp32 and the rp2040 debug ports broken out on
HE10-1.27mm headers (or pads if space is tight), I'm interested to get
one :)
The internal wifi antenna close to the IO header metal pins is also not
RF-optimal. Your version 2 was better on this aspect.
Also another suggestion, a large user flash available on esp32 or rp2040
spi gpios would be very useful for data logging and storage. Using the
esp32 code flash for this is not the best design. The 2KB fram is good
for parameter storage but is quite limited, no useful FS can be mounted
on it.
Best regards,
Sébastien
Le 26/10/2022 à 08:57, michael.sch...@mdc-service.de a écrit :
Dear Nuttx developers,
we have developed the EsPiff (ESP32+RP2040 on the Raspberry Pi Form
Factor), a open source board to replace RasPi's and there clones,
where the high processing power and/or Linux is not needed, but
stability and the reuse of RasPi HATs are required.
The github home is https://github.com/MDCservice/EsPiFF
We will also offer the EsPiFF on CrowdSupply
https://www.crowdsupply.com/mdc-service-wittenburg-gmbh/espiff
We would like to send a few boards for free to Nuttx developers, to
improve Nuttx compatibility. Would there be interest?
A high level summary about the EsPiFF:
An ESP32-WROVER-I module with 16 MB Flash, 8 MB PSRAM is taking care
- wired Ethernet via a IP101 PHY,
- Wifi (need an external Wifi Antenna with uFL connector),
- 3 serial UARTs,
- one the 3 serial UARTs is used for programming via a CH340 USB-UART
chip, what can be enabled/disabled with jumpers,
- I2C port expander PCA 9557 for some chip select signals and 3 user
LEDs,
- SDcard in SPI mode,
- external real time clock, with supervisior,
- 2kB FRAM,
- USB Type-C connector for up to 5V/3A, connected to the CH340
USB-UART to program the ESP32
An RP2040 (Pi Pico) what takes care the 40 pin RasPi header,
- connected to the ESP32 via SPI,
- UAB-A connector, also used to program the RP2040 (need to hold the
boot button while power the board).
In earlier versions, we had the LAN8720 PHY, but as others (Olimex,
wESP) we also got problems and replaced it with the IP101 since v3.1.
Currently, there is no HW debugging broken out on the board. But we
could add a JTAG header on the bottom side, with TDO, TDI, TCK, TMS,
GND, 3V3 in the next board production run. The ESP32 has the JTAG pins
on GPIO12, 13, 14, 15, what are used for SPI on the EsPiFF, so code
using the SPI could not be debugged while JTAG is using the pins.
Would it still make sense to build in the JTAG header?
Would be glad to get your feedback,
Michael
