On Wed, Jul 14, 2021 at 4:37 PM Nathan Hartman <hartman.nat...@gmail.com> wrote: > > Regarding STM32 EXTI register offsets in: > arch/arm/src/stm32/hardware/stm32_exti.h > > [[[ > > /* Register Offsets *********************************************************/ > > #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) > # define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ > # define STM32_EXTI2_OFFSET 0x0018 /* Offset to EXTI2 registers */ > #endif > > #define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ > #define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ > #define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register > */ > #define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection > register */ > #define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register > */ > #define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ > > ]]] > > Is STM32_EXTI2_OFFSET wrong or am I misunderstanding something? > > For reference, I am looking at the reference manuals for STM32F334xx > (RM0364 rev 4) and STM32F302xx (RM0365 rev 8), and both of these have > the IMR2 register offset at 0x20, EMR2 at 0x24, etc. > > It is easy to change this define, however, this define is here since > commit # ad9155eb16b7196ab3f27b0171cbb3f53bde72ce which is from 2013. > Perhaps the value 0x18 might be written here because it is correct for > some chip out there? > > Thanks, > Nathan
I submitted PR-4214 [1] to fix this offset; please check carefully, since I do not have hardware available to verify this change, but this change is based on the current reference manuals listed below: STM32F302xx: RM0365 rev 8, table 42 on page 229: https://www.st.com/resource/en/reference_manual/rm0365-stm32f302xbcde-and-stm32f302x68-advanced-armbased-32bit-mcus-stmicroelectronics.pdf STM32F334xx: RM0364 rev 4, table 36 on page 208: https://www.st.com/resource/en/reference_manual/rm0364-stm32f334xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf If you know of any affected SoC that does have 0x18 offset between EXTI1 and EXTI2, please let me know. [1] https://github.com/apache/incubator-nuttx/pull/4214 Cheers, Nathan
