The DBGMCU_APB1_FZ bit persists over regular software resets until
next POR-reset. It can impact device power consumption and things that
persist over resets are a bane for FOTA updates so make it disabled
by default.
OpenOCD sets this via DAP when connecting to target so enabling this
from Kconfig is only useful for users of some other debug tooling.
Best Regards,
Juha Niskanen
From 4dba47a74e932cb9af0965b6ffd3c3ae24592d5b Mon Sep 17 00:00:00 2001
From: Juha Niskanen <juha.niska...@haltian.com>
Date: Fri, 6 Mar 2020 09:51:11 +0200
Subject: [PATCH] arch/arm/src/stm32l4/stm32l4_iwdg.c: do not unconditionally
enable debug bits
The DBGMCU_APB1_FZ bit persists over regular software resets until
next POR-reset. It can impact device power consumption and things that
persist over resets are a bane for FOTA updates so make it disabled
by default.
OpenOCD sets this via DAP when connecting to target so enabling this
from Kconfig is only useful for users of some other debug tooling.
---
arch/arm/src/stm32l4/Kconfig | 20 ++++++++++++++++++++
arch/arm/src/stm32l4/stm32l4_iwdg.c | 15 +++++++++++----
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig
index 8ffdefd..85590c3 100644
--- a/arch/arm/src/stm32l4/Kconfig
+++ b/arch/arm/src/stm32l4/Kconfig
@@ -1666,6 +1666,26 @@ config STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
from one flash bank while writing on other flash bank. See your STM32
errata to check if your STM32 is affected by this problem.
+choice
+ prompt "JTAG Configuration"
+ default STM32L4_JTAG_DISABLE
+ ---help---
+ JTAG Enable settings (by default JTAG-DP and SW-DP are disabled)
+
+config STM32L4_JTAG_DISABLE
+ bool "Disable all JTAG clocking"
+
+config STM32L4_JTAG_FULL_ENABLE
+ bool "Enable full SWJ (JTAG-DP + SW-DP)"
+
+config STM32L4_JTAG_NOJNTRST_ENABLE
+ bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST"
+
+config STM32L4_JTAG_SW_ENABLE
+ bool "Set JTAG-DP disabled and SW-DP enabled"
+
+endchoice
+
config STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG
bool "Disable IDLE Sleep (WFI) in debug mode"
default n
diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c
index a4542a4..7749e38 100644
--- a/arch/arm/src/stm32l4/stm32l4_iwdg.c
+++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c
@@ -610,7 +610,6 @@ static int stm32l4_settimeout(FAR struct watchdog_lowerhalf_s *lower,
void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
{
FAR struct stm32l4_lowerhalf_s *priv = &g_wdgdev;
- uint32_t cr;
wdinfo("Entry: devpath=%s lsifreq=%d\n", devpath, lsifreq);
@@ -650,9 +649,17 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
* on DBG_IWDG_STOP configuration bit in DBG module.
*/
- cr = getreg32(STM32_DBGMCU_APB1_FZ);
- cr |= DBGMCU_APB1_IWDGSTOP;
- putreg32(cr, STM32_DBGMCU_APB1_FZ);
+#if defined(CONFIG_STM32L4_JTAG_FULL_ENABLE) || \
+ defined(CONFIG_STM32L4_JTAG_NOJNTRST_ENABLE) || \
+ defined(CONFIG_STM32L4_JTAG_SW_ENABLE)
+ {
+ uint32_t cr;
+
+ cr = getreg32(STM32_DBGMCU_APB1_FZ);
+ cr |= DBGMCU_APB1_IWDGSTOP;
+ putreg32(cr, STM32_DBGMCU_APB1_FZ);
+ }
+#endif
}
#endif /* CONFIG_WATCHDOG && CONFIG_STM32L4_IWDG */
--
2.7.4
