Dear Madams and Sirs, new attempt with a renamed patch file. If this is filtered again, I will follow Xiang's advice and post to https://github.com/apache/incubator-nuttx/pulls Best regards, Otmar
On 2020/02/22 06:12:04, Xiang Xiao <x...@gmail.com> wrote: > The attachment may be filtered by apache server, please submit a PR to:> > https://github.com/apache/incubator-nuttx/pulls> > Or change the patch suffix and resend again.> > > Thanks> > Xiang> > > On Sat, Feb 22, 2020 at 5:33 AM GOERLITZ Otmar> > <ot...@hexagon.com> wrote:> > >> > > Dear Madams and Sirs,> > >> > >> > >> > > the file arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h of NuttX 8.2. (as > > of 2020-02-21) appears to contain some incorrect definitions for RCC_CFGR3 > > register.> > >> > > Please consider the attached patch.> > >> > >> > >> > > Best regards,> > >> > > Otmar> > >> > >> > >> > > Otmar Görlitz> > >> > > Embedded Software Developer> > > T: +41 41 729 87 64> > > E: otmar.goerl...@hexagon.com> > >> > > Hexagon Mining> > > Baarerstrasse 133> > > 6300 Zug, Switzerland> > > hexagonmining.com | LinkedIn | Facebook | Twitter> > >> > >> >
From 6a613ae8a93e6450ab364b687e9041f9439e5af2 Mon Sep 17 00:00:00 2001 From: GOERLITZ Otmar <otmar.goerl...@hexagon.com> Date: Fri, 21 Feb 2020 15:09:22 +0100 Subject: [PATCH] STM32F30xxx RCC_CFGR3 header correction --- arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h index 0d4427fd0a..4c19a52de8 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h +++ b/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h @@ -357,14 +357,17 @@ # define RCC_CFGR2_ADC34PRESd128 (26 << RCC_CFGR2_ADC34PRES_SHIFT) /* 11010: PLL clock divided by 128 */ # define RCC_CFGR2_ADC34PRESd256 (27 << RCC_CFGR2_ADC34PRES_SHIFT) /* 11011: PLL clock divided by 256 */ -/* Clock configuration register 2 */ +/* Clock configuration register 3 */ -#define RCC_CFGR3_USART1SW_SHIFT (9) /* Bits 0-1: USART1 clock source selection */ +/* otmar.goerl...@hexagon.com, 2020-02-21: bit shift for USART1SW is 0; + * HSI bit pattern for all USARTxSW is 3 + */ +#define RCC_CFGR3_USART1SW_SHIFT (0) /* Bits 0-1: USART1 clock source selection */ #define RCC_CFGR3_USART1SW_MASK (3 << RCC_CFGR3_USART1SW_SHIFT) # define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) /* PCLK */ # define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) /* System clock (SYSCLK) */ # define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) /* LSE clock */ -# define RCC_CFGR3_USART1SW_HSI (0 << RCC_CFGR3_USART1SW_SHIFT) /* HSI clock */ +# define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT) /* HSI clock */ #define RCC_CFGR3_I2C1SW (1 << 4) /* Bit 4: I2C1 clock source selection */ #define RCC_CFGR3_I2C2SW (1 << 5) /* Bit 5: I2C2 clock source selection */ #define RCC_CFGR3_TIM1SW (1 << 8) /* Bit 8: Timer1 clock source selection */ @@ -374,24 +377,25 @@ # define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK */ # define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) /* System clock (SYSCLK) */ # define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) /* LSE clock */ -# define RCC_CFGR3_USART2SW_HSI (0 << RCC_CFGR3_USART2SW_SHIFT) /* HSI clock */ +# define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) /* HSI clock */ #define RCC_CFGR3_USART3SW_SHIFT (18) /* Bits 18-19: USART3 clock source selection */ #define RCC_CFGR3_USART3SW_MASK (3 << RCC_CFGR3_USART3SW_SHIFT) # define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART3SW_SHIFT) /* PCLK */ # define RCC_CFGR3_USART3SW_SYSCLK (1 << RCC_CFGR3_USART3SW_SHIFT) /* System clock (SYSCLK) */ # define RCC_CFGR3_USART3SW_LSE (2 << RCC_CFGR3_USART3SW_SHIFT) /* LSE clock */ -# define RCC_CFGR3_USART3SW_HSI (0 << RCC_CFGR3_USART3SW_SHIFT) /* HSI clock */ +# define RCC_CFGR3_USART3SW_HSI (3 << RCC_CFGR3_USART3SW_SHIFT) /* HSI clock */ #define RCC_CFGR3_UART4SW_SHIFT (20) /* Bits 20-21: UART4 clock source selection */ #define RCC_CFGR3_UART4SW_MASK (3 << RCC_CFGR3_UART4SW_SHIFT) # define RCC_CFGR3_UART4SW_PCLK (0 << RCC_CFGR3_UART4SW_SHIFT) /* PCLK */ # define RCC_CFGR3_UART4SW_SYSCLK (1 << RCC_CFGR3_UART4SW_SHIFT) /* System clock (SYSCLK) */ # define RCC_CFGR3_UART4SW_LSE (2 << RCC_CFGR3_UART4SW_SHIFT) /* LSE clock */ -# define RCC_CFGR3_UART4SW_HSI (0 << RCC_CFGR3_UART4SW_SHIFT) /* HSI clock */ +# define RCC_CFGR3_UART4SW_HSI (3 << RCC_CFGR3_UART4SW_SHIFT) /* HSI clock */ #define RCC_CFGR3_UART5SW_SHIFT (22) /* Bits 22-23: UART5 clock source selection */ #define RCC_CFGR3_UART5SW_MASK (3 << RCC_CFGR3_UART5SW_SHIFT) # define RCC_CFGR3_UART5SW_PCLK (0 << RCC_CFGR3_UART5SW_SHIFT) /* PCLK */ # define RCC_CFGR3_UART5SW_SYSCLK (1 << RCC_CFGR3_UART5SW_SHIFT) /* System clock (SYSCLK) */ # define RCC_CFGR3_UART5SW_LSE (2 << RCC_CFGR3_UART5SW_SHIFT) /* LSE clock */ -# define RCC_CFGR3_UART5SW_HSI (0 << RCC_CFGR3_UART5SW_SHIFT) /* HSI clock */ +# define RCC_CFGR3_UART5SW_HSI (3 << RCC_CFGR3_UART5SW_SHIFT) /* HSI clock */ #endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_RCC_H */ + -- 2.17.1
